/***************************************************************** * * Interface query functions * */ IxEthAccStatus ixEthAccMdioShow (void) { UINT32 regval; if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) { return (IX_ETH_ACC_FAIL); } ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); ixEthAccMdioCmdRead(®val); ixOsalMutexUnlock(&miiAccessLock); printf("MDIO command register\n"); printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31); printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26); printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f); printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f); ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); ixEthAccMdioStatusRead(®val); ixOsalMutexUnlock(&miiAccessLock); printf("MDIO status register\n"); printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31); printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff); return IX_ETH_ACC_SUCCESS; }
/********************************************************************* * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY */ IxEthAccStatus ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value) { UINT32 mdioCommand; UINT32 regval; UINT16 readVal; UINT32 miiTimeout; if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) { return (IX_ETH_ACC_FAIL); } if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) { return (IX_ETH_ACC_FAIL); } /* ensure that a PHY is present at this address */ if(ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, &readVal) != IX_ETH_ACC_SUCCESS) { return (IX_ETH_ACC_FAIL); } ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ; mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value; ixEthAccMdioCmdWrite(mdioCommand); miiTimeout = ixEthAccMiiRetryCount; while(miiTimeout) { ixEthAccMdioCmdRead(®val); /*The "GO" bit is reset to 0 when the write completes*/ if((regval & IX_ETH_ACC_MII_GO) == 0x0) { break; } /* Sleep for a while */ ixOsalSleep(ixEthAccMiiAccessTimeout); miiTimeout--; } ixOsalMutexUnlock(&miiAccessLock); if(miiTimeout == 0) { return IX_ETH_ACC_FAIL; } return IX_ETH_ACC_SUCCESS; }
PUBLIC void ixEthAccUnload(void) { IxEthAccPortId portId; if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) { /* check none of the port is still active */ for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) { if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) { if (ixEthAccMacState[portId].portDisableState == ACTIVE) { IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0); return; } } } /* unmap the memory areas */ ixEthAccMiiUnload(); ixEthAccMacUnload(); /* set all ports as uninitialized */ for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) { ixEthAccPortData[portId].portInitialized = FALSE; } /* uninitialize the service */ ixEthAccServiceInit = FALSE; } }
PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) { IxEthAccStatus ret=IX_ETH_ACC_SUCCESS; if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) { return(IX_ETH_ACC_FAIL); } /* * Check for valid port */ if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) ) { return (IX_ETH_ACC_INVALID_PORT); } if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) { IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0); return IX_ETH_ACC_SUCCESS ; } if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) { /* Already initialized */ return(IX_ETH_ACC_FAIL); } if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS) { return IX_ETH_ACC_FAIL; } /* * Set the port init flag. */ ixEthAccPortData[portId].portInitialized = TRUE; #ifdef CONFIG_IXP425_COMPONENT_ETHDB /* init learning/filtering database structures for this port */ ixEthDBPortInit(portId); #endif return(ret); }
/********************************************************************* * ixEthAccMiiReadRtn - read a 16 bit value from a PHY */ IxEthAccStatus ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value) { UINT32 mdioCommand; UINT32 regval; UINT32 miiTimeout; if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) { return (IX_ETH_ACC_FAIL); } if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) { return (IX_ETH_ACC_FAIL); } if (value == NULL) { return (IX_ETH_ACC_FAIL); } ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL | phyAddr << IX_ETH_ACC_MII_ADDR_SHL; mdioCommand |= IX_ETH_ACC_MII_GO; ixEthAccMdioCmdWrite(mdioCommand); miiTimeout = ixEthAccMiiRetryCount; while(miiTimeout) { ixEthAccMdioCmdRead(®val); if((regval & IX_ETH_ACC_MII_GO) == 0x0) { break; } /* Sleep for a while */ ixOsalSleep(ixEthAccMiiAccessTimeout); miiTimeout--; } if(miiTimeout == 0) { ixOsalMutexUnlock(&miiAccessLock); *value = 0xffff; return IX_ETH_ACC_FAIL; } ixEthAccMdioStatusRead(®val); if(regval & IX_ETH_ACC_MII_READ_FAIL) { ixOsalMutexUnlock(&miiAccessLock); *value = 0xffff; return IX_ETH_ACC_FAIL; } *value = regval & 0xffff; ixOsalMutexUnlock(&miiAccessLock); return IX_ETH_ACC_SUCCESS; }