/* ** Configures arm/dsp interrupt controller to generate frame interrupt */ static void SetupIntc(void) { #ifdef _TMS320C6X /* Initialize the DSP interrupt controller */ IntDSPINTCInit(); /* Register VPIF ISR to vector table */ IntRegister(C674X_MASK_INT5, VPIFIsr); /* Map system interrupt to DSP maskable interrupt for VPIF */ IntEventMap(C674X_MASK_INT5, SYS_INT_VPIF_INT); /* Enable DSP maskable interrupt for VPIF */ IntEnable(C674X_MASK_INT5); /* Register LCD ISR to vector table */ IntRegister(C674X_MASK_INT6, LCDIsr); /* Map system interrupt to DSP maskable interrupt for LCD */ IntEventMap(C674X_MASK_INT6, SYS_INT_LCDC_INT); /* Enable DSP maskable interrupt for LCD */ IntEnable(C674X_MASK_INT6); /* Enable DSP interrupts */ IntGlobalEnable(); #else /* Initialize the ARM Interrupt Controller.*/ IntAINTCInit(); /* Register the ISR in the Interrupt Vector Table.*/ IntRegister(SYS_INT_VPIF, VPIFIsr); /* Set the channel number 2 of AINTC for LCD system interrupt. */ IntChannelSet(SYS_INT_VPIF, 2); /* Enable the System Interrupts for AINTC.*/ IntSystemEnable(SYS_INT_VPIF); /* Register the ISR in the Interrupt Vector Table.*/ IntRegister(SYS_INT_LCDINT, LCDIsr); /* Set the channnel number 2 of AINTC for LCD system interrupt. */ IntChannelSet(SYS_INT_LCDINT, 3); /* Enable the System Interrupts for AINTC.*/ IntSystemEnable(SYS_INT_LCDINT); /* Enable IRQ in CPSR.*/ IntMasterIRQEnable(); /* Enable the interrupts in GER of AINTC.*/ IntGlobalEnable(); /* Enable the interrupts in HIER of AINTC.*/ IntIRQEnable(); #endif }
/* ** configures arm interrupt controller to generate PWM interrupts */ static void SetupIntc(void) { #ifdef _TMS320C6X // Initialize the DSP interrupt controller IntDSPINTCInit(); // Register the ISRs to the vector table IntRegister(C674X_MASK_INT4, PWMEventIsr); IntRegister(C674X_MASK_INT5, PWMTZIsr); // Map system events to the DSP maskable interrupts IntEventMap(C674X_MASK_INT4, SYS_INT_EHRPWM1); IntEventMap(C674X_MASK_INT5, SYS_INT_EHRPWM1TZ); // Enable the DSP maskable interrupts IntEnable(C674X_MASK_INT4); IntEnable(C674X_MASK_INT5); // Enable DSP interrupts globally IntGlobalEnable(); #else /* 실행x /* Initialize the ARM Interrupt Controller.* IntAINTCInit(); IntSystemStatusClear(SYS_INT_EHRPWM1); EHRPWMETIntClear(SOC_EHRPWM_1_REGS); /************************PWM1**************************************** IntRegister(SYS_INT_EHRPWM1, PWMEventIsr); IntChannelSet(SYS_INT_EHRPWM1, 2); IntSystemEnable(SYS_INT_EHRPWM1); /******************************************************************** IntRegister(SYS_INT_EHRPWM1TZ, PWMTZIsr); IntChannelSet(SYS_INT_EHRPWM1TZ, 2); IntSystemEnable(SYS_INT_EHRPWM1TZ); /******************************************************************** /* Enable IRQ in CPSR.* IntMasterIRQEnable(); /* Enable the interrupts in GER of AINTC.* IntGlobalEnable(); /* Enable the interrupts in HIER of AINTC.* IntIRQEnable(); */ #endif }
/* ** configures arm interrupt controller to generate raster interrupt */ void SetupIntc(void) { #ifdef _TMS320C6X IntDSPINTCInit(); IntRegister(C674X_MASK_INT4, LCDIsr); IntEventMap(C674X_MASK_INT4, SYS_INT_LCDC_INT); IntEnable(C674X_MASK_INT4); IntGlobalEnable(); #else /* Initialize the ARM Interrupt Controller.*/ IntAINTCInit(); /* Register the ISR in the Interrupt Vector Table.*/ IntRegister(SYS_INT_LCDINT, LCDIsr); /* Set the channnel number 2 of AINTC for LCD system interrupt. */ IntChannelSet(SYS_INT_LCDINT, 2); /* Enable the System Interrupts for AINTC.*/ IntSystemEnable(SYS_INT_LCDINT); IntSystemEnable(SYS_INT_I2CINT0); /* Enable IRQ in CPSR.*/ IntMasterIRQEnable(); /* Enable the interrupts in GER of AINTC.*/ IntGlobalEnable(); /* Enable the interrupts in HIER of AINTC.*/ IntIRQEnable(); #endif }
/* ** Sets up the interrupts for EDMA in AINTC */ static void EDMA3IntSetup(void) { #ifdef _TMS320C6X IntRegister(C674X_MASK_INT5, EDMA3CCComplIsr); IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_INT1); IntEnable(C674X_MASK_INT5); #else IntRegister(SYS_INT_CCINT0, EDMA3CCComplIsr); IntChannelSet(SYS_INT_CCINT0, INT_CHANNEL_EDMACC); IntSystemEnable(SYS_INT_CCINT0); #endif }
/* ** Sets up the I2C interrupt in the AINTC */ void I2C0IntRegister(unsigned int channel) { #ifdef _TMS320C6X IntRegister(C674X_MASK_INT5, I2C0Isr); IntEventMap(C674X_MASK_INT5, SYS_INT_I2C0_INT); IntEnable(C674X_MASK_INT5); #else /* Register the ISR in the Interrupt Vector Table.*/ IntRegister(SYS_INT_I2CINT0, I2C0Isr); IntChannelSet(SYS_INT_I2CINT0, channel); #endif }
/* ** Sets up the I2C interrupt in the AINTC */ static void I2CCodecIntSetup(unsigned int sysIntNum, unsigned int channel) { #ifdef _TMS320C6X IntRegister(C674X_MASK_INT4, I2CCodecIsr); IntEventMap(C674X_MASK_INT4, sysIntNum); IntEnable(C674X_MASK_INT4); #else /* Register the ISR in the Interrupt Vector Table.*/ IntRegister(sysIntNum, I2CCodecIsr); IntChannelSet(sysIntNum, channel); IntSystemEnable(sysIntNum); #endif }
/* ** Sets up the error interrupts for McASP in AINTC */ static void McASPErrorIntSetup(void) { #ifdef _TMS320C6X IntRegister(C674X_MASK_INT6, McASPErrorIsr); IntEventMap(C674X_MASK_INT6, SYS_INT_MCASP0_INT); IntEnable(C674X_MASK_INT6); #else /* Register the error ISR for McASP */ IntRegister(SYS_INT_MCASPINT, McASPErrorIsr); IntChannelSet(SYS_INT_MCASPINT, INT_CHANNEL_MCASP); IntSystemEnable(SYS_INT_MCASPINT); #endif }
static void EDMA3AINTCConfigure(void) { #if DEBUG_PRINT UARTprintf("%s()\r\n", __FUNCTION__); #endif /* Initialize DSP interrupt controller */ IntDSPINTCInit(); IntRegister(C674X_MASK_INT4, Edma3CompletionIsr); IntRegister(C674X_MASK_INT5, Edma3CCErrorIsr); IntEventMap(C674X_MASK_INT4, SYS_INT_EDMA3_0_CC0_INT1); IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_ERRINT); IntEnable(C674X_MASK_INT4); IntEnable(C674X_MASK_INT5); IntRegister(C674X_MASK_INT6, MMCSDIsr); IntEventMap(C674X_MASK_INT6, SYS_INT_MMCSD0_INT0); IntEnable(C674X_MASK_INT6); /* Enable DSP interrupts globally */ IntGlobalEnable(); }
static void ConfigureIntUART(void) { #ifdef _TMS320C6X IntRegister(C674X_MASK_INT4, UARTIsr); IntEventMap(C674X_MASK_INT4, SYS_INT_UART2_INT); IntEnable(C674X_MASK_INT4); #else /* Registers the UARTIsr in the Interrupt Vector Table of AINTC. */ IntRegister(SYS_INT_UARTINT2, UARTIsr); /* Map the channel number 2 of AINTC to UART2 system interrupt. */ IntChannelSet(SYS_INT_UARTINT2, 2); IntSystemEnable(SYS_INT_UARTINT2); #endif }
/* ** Set up the ARM Interrupt Controller for generating timer interrupt */ static void TimerIntrSetUp(void) { #ifdef _TMS320C6X /* Initialize the DSPINTC */ IntDSPINTCInit(); /* Register the Timer ISR */ IntRegister(C674X_MASK_INT4, TimerIsr); /* Map Timer interrupts to DSP maskable interrupt */ IntEventMap(C674X_MASK_INT4, SYS_INT_T64P2_TINTALL); /* Enable DSP interrupt in DSPINTC */ IntEnable(C674X_MASK_INT4); /* Enable DSP interrupts */ IntGlobalEnable(); #else /* Initialize AINTC and register timer interrupt */ IntAINTCInit(); /* Register the Timer ISR */ IntRegister(SYS_INT_TIMR2_ALL, TimerIsr); /* Set the channel number for Timer interrupt, it will map to IRQ */ IntChannelSet(SYS_INT_TIMR2_ALL, 2); /* Enable IRQ for ARM (in CPSR)*/ IntMasterIRQEnable(); /* Enable AINTC interrupts in GER */ IntGlobalEnable(); /* Enable IRQ in AINTC */ IntIRQEnable(); /* Enable timer interrupts in AINTC */ IntSystemEnable(SYS_INT_TIMR2_ALL); #endif }
static void ConfigureDSPINTCIntUSB (void) { IntRegister(4, USB0HostIntHandler); IntEventMap(4, SYS_INT_USB0); IntEnable(4); }