int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue
{
if(InterruptHdl == NULL)
{
//De-register Interprocessor communication interrupt between App and NWP
#ifdef SL_PLATFORM_MULTI_THREADED
osi_InterruptDeRegister(INT_NWPIC);
#else
IntDisable(INT_NWPIC);
IntUnregister(INT_NWPIC);
IntPendClear(INT_NWPIC);
#endif
g_pHostIntHdl = NULL;
}
else
{
g_pHostIntHdl = InterruptHdl;
#if 0
//Setting the 14th and 13th bit to '01' to make the HOST_IRQ edge triggered
HWREG(0x4402E168) |= 0x2000;
#endif
#ifdef SL_PLATFORM_MULTI_THREADED
IntPendClear(INT_NWPIC);
osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)HostIntHanlder,INT_PRIORITY_LVL_1);
#else
IntRegister(INT_NWPIC, HostIntHanlder);
IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
IntPendClear(INT_NWPIC);
IntEnable(INT_NWPIC);
#endif
}
return 0;
}
//*****************************************************************************
//
// Implementations of function that are required by usb framework.
//
//*****************************************************************************
void usbsuspHookEnteringSuspend(bool remoteWakeupAllowed) {
if (remoteWakeupAllowed) {
GPIOPowIntClear(BSP_KEY_SEL_BASE, BSP_KEY_SELECT);
GPIOPowIntEnable(BSP_KEY_SEL_BASE, BSP_KEY_SELECT);
IntPendClear(INT_GPIOA);
IntEnable(INT_GPIOA);
GPIOPowIntClear(BSP_KEY_DIR_BASE, BSP_KEY_DIR_ALL);
GPIOPowIntEnable(BSP_KEY_DIR_BASE, BSP_KEY_DIR_ALL);
IntPendClear(INT_GPIOC);
IntEnable(INT_GPIOC);
}
}
void Uart::interruptHandler(void)
{
uint32_t status;
// Read interrupt source
status = UARTIntStatus(uart_.base, true);
// Clear UART interrupt in the NVIC
IntPendClear(uart_.interrupt);
// Process TX interrupt
if (status & UART_INT_TX)
{
UARTIntClear(uart_.base, UART_INT_TX);
interruptHandlerTx();
}
// Process RX interrupt
if (status & UART_INT_RX ||
status & UART_INT_RT)
{
UARTIntClear(uart_.base, UART_INT_RX | UART_INT_RT);
interruptHandlerRx();
}
}
/**************************************************************************//**
* @brief Function enables 32 kHz timer interrupt.
*
* @return None
******************************************************************************/
void halTimer32kIntEnable(void)
{
// Clear pending interrupts
IntPendClear(INT_SMTIM);
// Enable interrupt
IntEnable(INT_SMTIM);
}
/**************************************************************************//**
* @brief Restart 32 kHz timer. Timer interval is set using halTimer32kInit().
*
* @return None
******************************************************************************/
void halTimer32kRestart(void)
{
// Set sleep mode timer compare value
SleepModeTimerCompareSet((SleepModeTimerCountGet()+ulHalTimer32kInterval));
// Clear pending interrupts
IntPendClear(INT_SMTIM);
}
/**************************************************************************************************
* @fn macMcuRfIsr
*
* @brief Interrupt service routine that handles all RF interrupts. There are a number
* of conditions "ganged" onto this one ISR so each condition must be tested for.
*
* @param none
*
* @return none
**************************************************************************************************
*/
void macMcuRfIsr(void)
{
uint8 rfim;
rfim = (uint8)RFIRQM1;
/* The CPU level RF interrupt flag must be cleared here (before clearing RFIRQFx).
* to allow the interrupts to be nested.
*/
IntPendClear(INT_RFCORERTX);
if ((RFIRQF1 & IRQ_CSP_MANINT) & ((uint32)rfim))
{
/*
* Important! Because of how the CSP programs are written, CSP_INT interrupts should
* be processed before CSP_STOP interrupts. This becomes an issue when there are
* long critical sections.
*/
/* clear flag */
RFIRQF1 = ~IRQ_CSP_MANINT;
macCspTxIntIsr();
}
else if ((RFIRQF1 & IRQ_CSP_STOP) & ((uint32)rfim))
{
/* clear flag */
RFIRQF1 = ~IRQ_CSP_STOP;
macCspTxStopIsr();
}
else if ((RFIRQF1 & IRQ_TXACKDONE) & ((uint32)rfim))
{
/* disable interrupt - set up is for "one shot" operation */
RFIRQM1 &= ~IM_TXACKDONE;
macRxAckTxDoneCallback();
}
rfim = (uint8)RFIRQM0;
/* process RFIRQF0 next */
if ((RFIRQF0 & IRQ_FIFOP) & ((uint32)rfim))
{
/* continue to execute interrup t handler as long as FIFOP is active */
do
{
macRxThresholdIsr();
RFIRQF0 = ~IRQ_FIFOP;
} while (FSMSTAT1 & FIFOP);
}
CLEAR_SLEEP_MODE();
}
void Spi::interruptHandler(void)
{
uint32_t status;
// Read interrupt source
status = SSIIntStatus(config_.base, true);
// Clear SPI interrupt in the NVIC
IntPendClear(config_.interrupt);
// Process TX interrupt
if (status & SSI_TXFF) {
interruptHandlerTx();
}
// Process RX interrupt
if (status & SSI_RXFF) {
interruptHandlerRx();
}
}
static void uart_isr_private(void){
uint32_t reg;
debugpins_isr_set();
// Read interrupt source
reg = UARTIntStatus(UART0_BASE, true);
// Clear UART interrupt in the NVIC
IntPendClear(INT_UART0);
// Process TX interrupt
if(reg & UART_INT_TX){
uart_tx_isr();
}
// Process RX interrupt
if((reg & (UART_INT_RX)) || (reg & (UART_INT_RT))) {
uart_rx_isr();
}
debugpins_isr_clr();
}
void bsp_timer_isr_private(void) {
debugpins_isr_set();
IntPendClear(INT_SMTIM);
bsp_timer_isr();
debugpins_isr_clr();
}
/*
* function: ADC3IntHandler
* interrupt handler ADC0, sequence 3
* return: none
* */
void ADC3IntHandler(void) {
unsigned long ulStatus;
static unsigned long uluDMACount = 0;
static unsigned long ulDataXferd = 0;
unsigned long ulNextuDMAXferSize = 0;
ADCIntClear(ADC0_BASE, SEQUENCER);
// If the channel's not done capturing, we have an error
if (uDMAChannelIsEnabled(UDMA_CHANNEL_ADC3)) {
// Increment error counter
adcNode[0].g_ulBadPeriphIsr2++;
ADCIntDisable(ADC0_BASE, SEQUENCER);
IntPendClear(INT_ADC0SS3);
return;
}
ulStatus = uDMAChannelSizeGet(UDMA_CHANNEL_ADC3);
// If non-zero items are left in the transfer buffer
// Something went wrong
if (ulStatus) {
adcNode[0].g_ulBadPeriphIsr1++;
return;
}
// Disable the sampling timer
TimerDisable(TIMER0_BASE, TIMER_A);
// how many times the DMA has been full without processing the data
uluDMACount++;
// The amount of data transferred increments in sets of 1024
ulDataXferd += UDMA_XFER_MAX;
if (NUM_SAMPLES > ulDataXferd) {
if ((NUM_SAMPLES - ulDataXferd) > UDMA_XFER_MAX) {
ulNextuDMAXferSize = UDMA_XFER_MAX;
} else {
ulNextuDMAXferSize = NUM_SAMPLES - ulDataXferd;
}
#ifdef USE_TEMPORARY_BUFFER
if (currentAdcBuffer == g_ulADCValues_B) {
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *) (ADC0_BASE + ADC_O_SSFIFO3 + (0x20 * UDMA_ARB_1)),
g_ulADCValues + (UDMA_XFER_MAX * uluDMACount),
ulNextuDMAXferSize);
} else {
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *) (ADC0_BASE + ADC_O_SSFIFO3 + (0x20 * UDMA_ARB_1)),
g_ulADCValues_B + (UDMA_XFER_MAX * uluDMACount),
ulNextuDMAXferSize);
}
#endif
#ifdef NOT_TEMPORARY_BUFFER
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *) (ADC0_BASE + ADC_O_SSFIFO3 + (0x20 * UDMA_ARB_1)),
g_ulADCValues + (UDMA_XFER_MAX * uluDMACount),
ulNextuDMAXferSize);
#endif
uDMAChannelEnable(UDMA_CHANNEL_ADC3);
TimerLoadSet(TIMER0_BASE, TIMER_A, LoadTimer);
TimerEnable(TIMER0_BASE, TIMER_A);
} else {
uluDMACount = 0;
ulDataXferd = 0;
ADCIntDisable(ADC0_BASE, SEQUENCER);
IntPendClear(INT_ADC0SS3);
// Signal that we have new data to be processed
adcNode[0].g_ucDataReady = 1;
#ifdef USING_BUFFER2
if (adcNode[0].g_ucDataReady) {
memcpy(output2, g_ulADCValues, NUM_SAMPLES);
countFullData++;
}
#endif
}
}
//*****************************************************************************
//
//! Start an AES-ECB operation (encryption or decryption).
//
//*****************************************************************************
uint32_t
CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
uint32_t ui32KeyLocation, bool bEncrypt,
bool bIntEnable)
{
//
// Set current operating state of the Crypto module.
//
g_ui32CurrentAesOp = CRYPTO_AES_ECB;
//
// Enable internal interrupts.
//
HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_INT_LEVEL;
HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
//
// Clear any outstanding interrupts.
//
HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
CRYPTO_IRQCLR_RESULT_AVAIL);
//
// If using interrupts clear any pending interrupts and enable interrupts
// for the Crypto module.
//
if(bIntEnable)
{
IntPendClear(INT_CRYPTO);
IntEnable(INT_CRYPTO);
}
//
// Configure Master Control module.
//
HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
//
//
//
HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
//
//Wait until key is loaded to the AES module.
//
do
{
CPUdelay(1);
}
while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
//
// Check for Key store Read error.
//
if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
{
return (AES_KEYSTORE_READ_ERROR);
}
//
// Configure AES engine (program AES-ECB-128 encryption and no
// initialization vector - IV).
//
if(bEncrypt)
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT;
}
else
{
HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT;
}
//
// Write the length of the data.
//
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH;
HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
//
// Enable Crypto DMA channel 0.
//
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0CTL) |= CRYPTO_DMACH0CTL_EN;
//
// Base address of the input data in ext. memory.
//
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;
//
// Input data length in bytes, equal to the message.
//
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH;
//
// Enable Crypto DMA channel 1.
//
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1CTL) |= CRYPTO_DMACH1CTL_EN;
//
// Setup the address and length of the output data.
//
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH;
//
// Return success
//
return AES_SUCCESS;
}
kick_scheduler_t radio_isr() {
volatile PORT_TIMER_WIDTH capturedTime;
uint8_t irq_status0,irq_status1;
// capture the time
capturedTime = radiotimer_getCapturedTime();
// reading IRQ_STATUS
irq_status0 = HWREG(RFCORE_SFR_RFIRQF0);
irq_status1 = HWREG(RFCORE_SFR_RFIRQF1);
IntPendClear(INT_RFCORERTX);
//clear interrupt
HWREG(RFCORE_SFR_RFIRQF0) = 0;
HWREG(RFCORE_SFR_RFIRQF1) = 0;
//STATUS0 Register
// start of frame event
if ((irq_status0 & RFCORE_SFR_RFIRQF0_SFD) == RFCORE_SFR_RFIRQF0_SFD) {
// change state
radio_vars.state = RADIOSTATE_RECEIVING;
if (radio_vars.startFrame_cb!=NULL) {
// call the callback
radio_vars.startFrame_cb(capturedTime);
// kick the OS
return KICK_SCHEDULER;
} else {
while(1);
}
}
//or RXDONE is full -- we have a packet.
if (((irq_status0 & RFCORE_SFR_RFIRQF0_RXPKTDONE) == RFCORE_SFR_RFIRQF0_RXPKTDONE)) {
// change state
radio_vars.state = RADIOSTATE_TXRX_DONE;
if (radio_vars.endFrame_cb!=NULL) {
// call the callback
radio_vars.endFrame_cb(capturedTime);
// kick the OS
return KICK_SCHEDULER;
} else {
while(1);
}
}
//or FIFOP is full -- we have a packet.
if (((irq_status0 & RFCORE_SFR_RFIRQF0_FIFOP) == RFCORE_SFR_RFIRQF0_FIFOP)) {
// change state
radio_vars.state = RADIOSTATE_TXRX_DONE;
if (radio_vars.endFrame_cb!=NULL) {
// call the callback
radio_vars.endFrame_cb(capturedTime);
// kick the OS
return KICK_SCHEDULER;
} else {
while(1);
}
}
//STATUS1 Register
// end of frame event --either end of tx .
if (((irq_status1 & RFCORE_SFR_RFIRQF1_TXDONE) == RFCORE_SFR_RFIRQF1_TXDONE)) {
// change state
radio_vars.state = RADIOSTATE_TXRX_DONE;
if (radio_vars.endFrame_cb!=NULL) {
// call the callback
radio_vars.endFrame_cb(capturedTime);
// kick the OS
return KICK_SCHEDULER;
} else {
while(1);
}
}
return DO_NOT_KICK_SCHEDULER;
}
/*
* function: ADC3IntHandler
* interrupt handler ADC0, sequence 3
* return: none
* */
void ADC3IntHandler(void) {
unsigned long ulStatus;
static unsigned long uluDMACount = 0;
static unsigned long ulDataXferd = 0;
unsigned long ulNextuDMAXferSize = 0;
unsigned short *pusDMABuffer;
unsigned short *pusCopyBuffer;
int i;
ADCIntClear(ADC0_BASE, SEQUENCER);
// If the channel's not done capturing, we have an error
if (uDMAChannelIsEnabled(UDMA_CHANNEL_ADC3)) {
// Increment error counter
adcNode[0].g_ulBadPeriphIsr2++;
ADCIntDisable(ADC0_BASE, SEQUENCER);
IntPendClear(INT_ADC0SS3);
return;
}
ulStatus = uDMAChannelSizeGet(UDMA_CHANNEL_ADC3);
// If non-zero items are left in the transfer buffer
// Something went wrong
if (ulStatus) {
adcNode[0].g_ulBadPeriphIsr1++;
return;
}
if (g_ucDMAMethod == DMA_METHOD_SLOW) {
//
// We are using the slow DMA method, meaning there are not enough
// samples in a second to generate a new set of FFT values and still
// have data frequent enough to refresh at 15 frames per second
//
//
// when pingpong is 0, uDMA just finished transferring into ping, so next
// we transfer into pong.
//
if (g_ucDMApingpong == 0) {
pusDMABuffer = g_usDMApong;
pusCopyBuffer = g_usDMAping;
g_ucDMApingpong = 1;
} else {
pusDMABuffer = g_usDMAping;
pusCopyBuffer = g_usDMApong;
g_ucDMApingpong = 0;
}
//
// Set up the next uDMA transfer
//
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, (void *) (ADC0_BASE + ADC_O_SSFIFO3),// + (0x20 * UDMA_ARB_1)),
pusDMABuffer, DMA_SIZE);
uDMAChannelEnable(UDMA_CHANNEL_ADC3);
IntPendClear(INT_ADC0SS3);
//
// Shift everything back DMA_SIZE samples
//
for (i = 0; i < (NUM_SAMPLES - DMA_SIZE); i++) {
g_ulADCValues[i] = g_ulADCValues[i + DMA_SIZE];
}
//
// Copy the new samples from the copy buffer into the sample array
//
for (i = 0; i < DMA_SIZE; i++) {
g_ulADCValues[i + NUM_SAMPLES - DMA_SIZE] = pusCopyBuffer[i];
}
//
// Signal that we have new data to be processed
//
adcNode[0].g_ucDataReady = 1;
} else {
// Disable the sampling timer
TimerDisable(TIMER0_BASE, TIMER_A);
// how many times the DMA has been full without processing the data
uluDMACount++;
// The amount of data transferred increments in sets of 1024
ulDataXferd += UDMA_XFER_MAX;
if (NUM_SAMPLES > ulDataXferd) {
if ((NUM_SAMPLES - ulDataXferd) > UDMA_XFER_MAX) {
ulNextuDMAXferSize = UDMA_XFER_MAX;
} else {
ulNextuDMAXferSize = NUM_SAMPLES - ulDataXferd;
}
#ifdef USE_TEMPORARY_BUFFER
if (currentAdcBuffer == g_ulADCValues_B) {
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *) (ADC0_BASE + ADC_O_SSFIFO3 + (0x20 * UDMA_ARB_1)),
g_ulADCValues + (UDMA_XFER_MAX * uluDMACount),
ulNextuDMAXferSize);
} else {
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *) (ADC0_BASE + ADC_O_SSFIFO3 + (0x20 * UDMA_ARB_1)),
g_ulADCValues_B + (UDMA_XFER_MAX * uluDMACount),
ulNextuDMAXferSize);
}
#endif
uDMAChannelTransferSet(UDMA_CHANNEL_ADC3 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *) (ADC0_BASE + ADC_O_SSFIFO3 + (0x20 * UDMA_ARB_1)),
g_ulADCValues + (UDMA_XFER_MAX * uluDMACount),
ulNextuDMAXferSize);
uDMAChannelEnable(UDMA_CHANNEL_ADC3);
TimerLoadSet(TIMER0_BASE, TIMER_A, LoadTimer);
TimerEnable(TIMER0_BASE, TIMER_A);
} else {
uluDMACount = 0;
ulDataXferd = 0;
ADCIntDisable(ADC0_BASE, SEQUENCER);
IntPendClear(INT_ADC0SS3);
// Signal that we have new data to be processed
adcNode[0].g_ucDataReady = 1;
#ifdef USING_BUFFER2
if (adcNode[0].g_ucDataReady) {
memcpy(output2, g_ulADCValues, NUM_SAMPLES);
countFullData++;
}
#endif
}
}
}
