/* Initialize VPR 1. Read Options 2. Read Arch 3. Read Circuit 4. Sanity check all three */ void vpr_init(INP int argc, INP char **argv, OUTP t_options *options, OUTP t_vpr_setup *vpr_setup, OUTP t_arch *arch) { char* pszLogFileName = "vpr_stdout.log"; unsigned char enableTimeStamps = 1; unsigned long maxWarningCount = 100000; unsigned long maxErrorCount = 1000; if (PrintHandlerExists() == 1) { has_printhandler_pre_vpr = TRUE; } else { has_printhandler_pre_vpr = FALSE; } if (has_printhandler_pre_vpr == FALSE) { PrintHandlerNew(pszLogFileName); PrintHandlerInit(enableTimeStamps, maxWarningCount, maxErrorCount); } /* Print title message */ vpr_print_title(); /* Print usage message if no args */ if (argc < 3) { vpr_print_usage(); exit(1); } memset(options, 0, sizeof(t_options)); memset(vpr_setup, 0, sizeof(t_vpr_setup)); memset(arch, 0, sizeof(t_arch)); /* Read in user options */ ReadOptions(argc, argv, options); /* Timing option priorities */ vpr_setup->TimingEnabled = IsTimingEnabled(options); /* Determine whether echo is on or off */ setEchoEnabled(IsEchoEnabled(options)); setDumpVtbEnabled(IsDumpVtbEnabled(options)); SetPostSynthesisOption(IsPostSynthesisEnabled(options)); vpr_setup->constant_net_delay = options->constant_net_delay; /* Read in arch and circuit */ SetupVPR(options, vpr_setup->TimingEnabled, TRUE, &vpr_setup->FileNameOpts, arch, &vpr_setup->Operation, &vpr_setup->user_models, &vpr_setup->library_models, &vpr_setup->PackerOpts, &vpr_setup->PlacerOpts, &vpr_setup->AnnealSched, &vpr_setup->RouterOpts, &vpr_setup->RoutingArch, &vpr_setup->Segments, &vpr_setup->Timing, &vpr_setup->ShowGraphics, &vpr_setup->GraphPause, &vpr_setup->PowerOpts); /* Check inputs are reasonable */ CheckOptions(*options, vpr_setup->TimingEnabled); CheckArch(*arch, vpr_setup->TimingEnabled); /* Verify settings don't conflict or otherwise not make sense */ CheckSetup(vpr_setup->Operation, vpr_setup->PlacerOpts, vpr_setup->AnnealSched, vpr_setup->RouterOpts, vpr_setup->RoutingArch, vpr_setup->Segments, vpr_setup->Timing, arch->Chans); /* flush any messages to user still in stdout that hasn't gotten displayed */ fflush(stdout); /* Read blif file and sweep unused components */ read_and_process_blif(vpr_setup->PackerOpts.blif_file_name, vpr_setup->PackerOpts.sweep_hanging_nets_and_inputs, vpr_setup->user_models, vpr_setup->library_models, vpr_setup->PowerOpts.do_power, vpr_setup->FileNameOpts.ActFile); fflush(stdout); ShowSetup(*options, *vpr_setup); }
int main(int argc, char **argv) { int simSize = 14; int xx; simResults = (double *) malloc(simSize*sizeof(double)); simCounts = (unsigned long *) malloc(simSize*sizeof(unsigned long)); simIndex = 0; for(xx = 0; xx < simSize ; xx++) { simResults[xx] = 0.0; simCounts[xx] = 0; } t_options Options; t_arch Arch = { 0 }; enum e_operation Operation; struct s_placer_opts PlacerOpts; struct s_annealing_sched AnnealSched; struct s_router_opts RouterOpts; struct s_det_routing_arch RoutingArch; t_segment_inf *Segments; t_timing_inf Timing; t_subblock_data Subblocks; boolean ShowGraphics; boolean TimingEnabled; int GraphPause; /* Print title message */ PrintTitle(); /* Print usage message if no args */ if(argc < 2) { PrintUsage(); exit(1); } /* Read in available inputs */ ReadOptions(argc, argv, &Options); /* Determine whether timing is on or off */ TimingEnabled = IsTimingEnabled(Options); /* Use inputs to configure VPR */ SetupVPR(Options, TimingEnabled, &Arch, &Operation, &PlacerOpts, &AnnealSched, &RouterOpts, &RoutingArch, &Segments, &Timing, &Subblocks, &ShowGraphics, &GraphPause); /* Check inputs are reasonable */ CheckOptions(Options, TimingEnabled); CheckArch(Arch, TimingEnabled); /* Verify settings don't conflict or otherwise not make sense */ CheckSetup(Operation, PlacerOpts, AnnealSched, RouterOpts, RoutingArch, Segments, Timing, Subblocks, Arch.Chans); /* Output the current settings to console. */ ShowSetup(Options, Arch, TimingEnabled, Operation, PlacerOpts, AnnealSched, RouterOpts, RoutingArch, Segments, Timing, Subblocks); if(Operation == TIMING_ANALYSIS_ONLY) { do_constant_net_delay_timing_analysis( Timing, Subblocks, Options.constant_net_delay); return 0; } /* Startup X graphics */ set_graphics_state(ShowGraphics, GraphPause, RouterOpts.route_type); if(ShowGraphics) { init_graphics("VPR: Versatile Place and Route for FPGAs"); alloc_draw_structs(); } /* Do the actual operation */ place_and_route(Operation, PlacerOpts, Options.PlaceFile, Options.NetFile, Options.ArchFile, Options.RouteFile, AnnealSched, RouterOpts, RoutingArch, Segments, Timing, &Subblocks, Arch.Chans); /* Close down X Display */ if(ShowGraphics) close_graphics(); /* free data structures */ free(Options.PlaceFile); free(Options.NetFile); free(Options.ArchFile); free(Options.RouteFile); freeArch(&Arch); printf("\nTiming Results\n"); for(xx = 0; xx < simSize ; xx++) { if(simCounts[xx] != 0) { simResults[xx] /= (double) simCounts[xx]; } printf("Index: %d\tAverage Clock: %f\n", xx, simResults[xx]); } free(simResults); free(simCounts); /* Return 0 to single success to scripts */ return 0; }