void
sys$sigma0_map_fpage(L4_Fpage_t virt_page, L4_Fpage_t phys_page,
unsigned int priv)
{
L4_ThreadId_t tid;
L4_MsgTag_t tag;
L4_Msg_t msg;
L4_MapItem_t map;
// Find Pager's ID
tid = L4_Pager();
L4_Set_Rights(&phys_page, priv);
L4_Accept(L4_MapGrantItems(virt_page));
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, (L4_Word_t) phys_page.raw);
L4_MsgAppendWord(&msg, (L4_Word_t) 0);
L4_Set_Label(&msg.tag, SIGMA0_REQUEST_LABEL);
L4_MsgLoad(&msg);
tag = L4_Call(tid);
PANIC(L4_IpcFailed(tag), notice(IPC_F_FAILED "IPC failed (error %ld: %s)\n",
L4_ErrorCode(), L4_ErrorCode_String(L4_ErrorCode())));
L4_MsgStore(tag, &msg);
L4_MsgGetMapItem(&msg, 0, &map);
if (dbg$virtual_memory == 1)
{
if (map.X.snd_fpage.raw == L4_Nilpage.raw)
{
notice(MEM_I_REJMAP "rejecting mapping\n");
notice(MEM_I_REJMAP "virtual $%016lX - $%016lX\n",
L4_Address(virt_page), L4_Address(virt_page)
+ (L4_Size(virt_page) - 1));
notice(MEM_I_REJMAP "physical $%016lX - $%016lX\n",
L4_Address(phys_page), L4_Address(phys_page)
+ (L4_Size(phys_page) - 1));
}
else
{
notice(MEM_I_ACCMAP "accepting mapping\n");
notice(MEM_I_ACCMAP "virtual $%016lX - $%016lX\n",
L4_Address(virt_page), L4_Address(virt_page)
+ (L4_Size(virt_page) - 1));
notice(MEM_I_ACCMAP "physical $%016lX - $%016lX\n",
L4_Address(phys_page), L4_Address(phys_page)
+ (L4_Size(phys_page) - 1));
}
}
return;
}
int
l4e_sigma0_map_fpage(L4_Fpage_t virt_page, L4_Fpage_t phys_page)
{
/*
* XXX: These two special cases are workarounds for broken superpage
* support in pistachio. On ARM, 1M superpages are disabled by
* pistachio to reduce the size of the mapping database, however due to
* bugs in the mapping code, any mappings >= 1M get converted into 4K
* mappings (rather than 64K). For MIPS, the tlb refill code assumes
* only 4K mappings are used, even the the pagetable building code will
* use superpages where possible. -- alexw
*/
#if defined(ARCH_ARM)
uintptr_t virt_base = L4_Address(virt_page);
uintptr_t phys_base = L4_Address(phys_page);
uintptr_t offset = 0;
uintptr_t step = L4_Size(virt_page) > 0x10000 ? 0x10000 : L4_Size(virt_page);
uintptr_t limit = L4_Size(virt_page) - 1;
for (virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step);
offset < limit;
offset += step,
virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step))
#elif defined(ARCH_MIPS64)
uintptr_t virt_base = L4_Address(virt_page);
uintptr_t phys_base = L4_Address(phys_page);
uintptr_t offset = 0;
uintptr_t step = 0x1000;
uintptr_t limit = L4_Size(virt_page) - 1;
for (virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step);
offset < limit;
offset += step,
virt_page = L4_Fpage(virt_base + offset, step),
phys_page = L4_Fpage(phys_base + offset, step))
#endif
{
L4_ThreadId_t tid;
L4_MsgTag_t tag;
L4_Msg_t msg;
L4_MapItem_t map;
/*
* find our pager's ID
*/
tid = L4_Pager();
L4_Set_Rights(&phys_page, L4_FullyAccessible);
/* accept fpages */
L4_Accept(L4_MapGrantItems(virt_page));
/* send it to our pager */
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, (L4_Word_t) phys_page.raw);
L4_MsgAppendWord(&msg, (L4_Word_t) 0);
L4_Set_Label(&msg.tag, SIGMA0_REQUEST_LABEL);
L4_MsgLoad(&msg);
/* make the call */
tag = L4_Call(tid);
/* check for an error */
if (L4_IpcFailed(tag)) {
return 2;
}
L4_MsgStore(tag, &msg);
L4_MsgGetMapItem(&msg, 0, &map);
/*
* rejected mapping?
*/
if (map.X.snd_fpage.raw == L4_Nilpage.raw) {
return 1;
}
}
return 0;
}
