static void uhci_fsbr_on(struct uhci_hcd *uhci) { struct uhci_qh *lqh; uhci->fsbr_is_on = 1; lqh = list_entry(uhci->skel_async_qh->node.prev, struct uhci_qh, node); lqh->link = LINK_TO_QH(uhci->skel_term_qh); }
/* * Full-Speed Bandwidth Reclamation (FSBR). * We turn on FSBR whenever a queue that wants it is advancing, * and leave it on for a short time thereafter. */ static void uhci_fsbr_on(struct uhci_hcd *uhci) { struct uhci_qh *lqh; /* The terminating skeleton QH always points back to the first * FSBR QH. Make the last async QH point to the terminating * skeleton QH. */ uhci->fsbr_is_on = 1; lqh = list_entry(uhci->skel_async_qh->node.prev, struct uhci_qh, node); lqh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); }
/* * Calculate the link pointer DMA value for the first Skeleton QH in a frame. */ static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) { int skelnum; /* * The interrupt queues will be interleaved as evenly as possible. * There's not much to be done about period-1 interrupts; they have * to occur in every frame. But we can schedule period-2 interrupts * in odd-numbered frames, period-4 interrupts in frames congruent * to 2 (mod 4), and so on. This way each frame only has two * interrupt QHs, which will help spread out bandwidth utilization. * * ffs (Find First bit Set) does exactly what we need: * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. * ffs >= 7 => not on any high-period queue, so use * period-1 QH = skelqh[9]. * Add in UHCI_NUMFRAMES to insure at least one bit is set. */ skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); if (skelnum <= 1) skelnum = 9; return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); }
static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) { int skelnum; /* */ skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); if (skelnum <= 1) skelnum = 9; return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); }