/** * @brief De-initialize registers of all ADC instances belonging to * the same ADC common instance to their default reset values. * @note This function is performing a hard reset, using high level * clock source RCC ADC reset. * Caution: On this STM32 family, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use * function @ref LL_ADC_DeInit(). * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC); /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC); return SUCCESS; }
/** * @brief De-initialize RNG registers (Registers restored to their default values). * @param RNGx RNG Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); /* Enable RNG reset state */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); /* Release RNG from reset state */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); return (SUCCESS); }
/** * @brief De-initialize GPIO registers (Registers restored to their default values). * @param GPIOx GPIO Port * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); /* Force and Release reset on clock of GPIOx Port */ if (GPIOx == GPIOA) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA); } else if (GPIOx == GPIOB) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB); } else if (GPIOx == GPIOC) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC); } #if defined(GPIOD) else if (GPIOx == GPIOD) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD); } #endif /* GPIOD */ #if defined(GPIOE) else if (GPIOx == GPIOE) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE); } #endif /* GPIOE */ #if defined(GPIOF) else if (GPIOx == GPIOF) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF); } #endif /* GPIOF */ #if defined(GPIOG) else if (GPIOx == GPIOG) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG); } #endif /* GPIOG */ #if defined(GPIOH) else if (GPIOx == GPIOH) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH); } #endif /* GPIOH */ #if defined(GPIOI) else if (GPIOx == GPIOI) { LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI); LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI); } #endif /* GPIOI */ else { status = ERROR; } return (status); }