/**
* @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
* @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0),
* UCPD IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param UCPDx UCPD Instance
* @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
* the configuration information for the UCPD peripheral.
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
*/
ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
{
/* Check the ucpd Instance UCPDx*/
assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
if(UCPD1 == UCPDx)
{
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD1);
}
if(UCPD2 == UCPDx)
{
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD2);
}
LL_UCPD_Disable(UCPDx);
/*---------------------------- UCPDx CFG1 Configuration ------------------------*/
MODIFY_REG(UCPDx->CFG1,
UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
UCPD_InitStruct->psc_ucpdclk | UCPD_InitStruct->transwin |
UCPD_InitStruct->IfrGap | UCPD_InitStruct->HbitClockDiv);
return SUCCESS;
}
static inline int stm32_clock_control_on(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
ARG_UNUSED(dev);
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_EnableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F4X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X */
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
#ifndef CONFIG_SOC_SERIES_STM32F0X
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32F0X */
}
return 0;
}
int usb_dc_attach(void)
{
int ret;
LOG_DBG("");
/*
* For STM32F0 series SoCs on QFN28 and TSSOP20 packages enable PIN
* pair PA11/12 mapped instead of PA9/10 (e.g. stm32f070x6)
*/
#if defined(DT_USB_ENABLE_PIN_REMAP)
if (LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_SYSCFG)) {
LL_SYSCFG_EnablePinRemap();
} else {
LOG_ERR("System Configuration Controller clock is "
"disable. Unable to enable pin remapping."
}
#endif
ret = usb_dc_stm32_clock_enable();
if (ret) {
return ret;
}
ret = usb_dc_stm32_init();
if (ret) {
return ret;
}
/*
* Required for at least STM32L4 devices as they electrically
* isolate USB features from VDDUSB. It must be enabled before
* USB can function. Refer to section 5.1.3 in DM00083560 or
* DM00310109.
*/
#ifdef PWR_CR2_USV
if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
LL_PWR_EnableVddUSB();
} else {
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
LL_PWR_EnableVddUSB();
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
}
#endif /* PWR_CR2_USV */
return 0;
}
void TI_TriggerInit(void)
{
uint32_t TIM2_clk;
/******************************/
/* Peripheral clocks enabling */
/******************************/
/* Enable the peripheral clock of GPIOs */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
/* Enable the peripheral clock of TIM2 */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
/*************************/
/* GPIO AF configuration */
/*************************/
/* GPIO TIM2_CH1 configuration */
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_5, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_5, LL_GPIO_PULL_DOWN);
LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_5, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_5, LL_GPIO_AF_1);
/* GPIO TIM2_CH2 configuration */
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_1, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_1, LL_GPIO_PULL_DOWN);
LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_1, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_1, LL_GPIO_AF_1);
/*******************************/
/* Input trigger configuration */
/*******************************/
/* Map TI2FP2 on TI2 */
LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_DIRECTTI);
/* TI2FP2 must detect a rising edge */
LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_POLARITY_RISING);
/* Configure TI2FP2 as trigger */
LL_TIM_SetTriggerInput(TIM2, LL_TIM_TS_TI2FP2);
/* Enable the slave mode controller: TI2FP2 is used to start the counter */
LL_TIM_SetSlaveMode(TIM2, LL_TIM_SLAVEMODE_TRIGGER);
/*********************************/
/* Output waveform configuration */
/*********************************/
/* Select counter mode: counting up */
LL_TIM_SetCounterMode(TIM2, LL_TIM_COUNTERMODE_UP);
/* Set the one pulse mode: generate only 1 pulse */
LL_TIM_SetOnePulseMode(TIM2, LL_TIM_ONEPULSEMODE_SINGLE);
/* In this example TIM2 input clock (TIM2CLK) is set to APB1 clock (PCLK1), */
/* since APB1 pre-scaler is equal to /2*2 = 1. */
/* TIM2CLK = PCLK1 */
/* PCLK1 = HCLK */
/* => TIM2CLK = SystemCoreClock (32 MHz) */
TIM2_clk = SystemCoreClock/1;
/* Set the TIM2 prescaler to get counter clock frequency at 2 kHz */
LL_TIM_SetPrescaler(TIM2, __LL_TIM_CALC_PSC(TIM2_clk, 2000));
/* Set the capture/compare register to get a pulse delay of 2s (2000000 us)*/
LL_TIM_OC_SetCompareCH1(TIM2, __LL_TIM_CALC_DELAY(TIM2_clk, LL_TIM_GetPrescaler(TIM2), 2000000));
/* Set the autoreload register to get a pulse length of 3s (3000000 us)*/
LL_TIM_SetAutoReload(TIM2, __LL_TIM_CALC_PULSE(TIM2_clk, LL_TIM_GetPrescaler(TIM2), 2000000, 3000000));
/* Set output channel 1 in PWM2 mode */
LL_TIM_OC_SetMode(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_PWM2);
/* Configure output channel 1 configuration */
LL_TIM_OC_ConfigOutput(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_OCPOLARITY_HIGH);
/**************************/
/* Start pulse generation */
/**************************/
/* Enable channel 1 */
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
/* Enable auto-reload register preload */
LL_TIM_EnableARRPreload(TIM2);
/* Force update generation */
LL_TIM_GenerateEvent_UPDATE(TIM2);
}
void spi_config(void)
{
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
LL_SPI_SetNSSMode(SPI2, LL_SPI_NSS_SOFT);
LL_SPI_SetMode(SPI2, LL_SPI_MODE_MASTER);
}