/** * @brief Return LPTIMx clock frequency * @param LPTIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_LPTIM1_CLKSOURCE * @retval LPTIM clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) { uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) { /* LPTIM1CLK clock frequency */ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ if (LL_RCC_LSI_IsReady()) { lptim_frequency = LSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { lptim_frequency = HSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { lptim_frequency = LSE_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ default: lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } return lptim_frequency; }
/** * @brief Disable the LPTIM instance * @rmtoll CR ENABLE LL_LPTIM_Disable * @param LPTIMx Low-Power Timer instance * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. * @retval None */ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) { LL_RCC_ClocksTypeDef rcc_clock; uint32_t tmpclksource = 0; uint32_t tmpIER; uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; uint32_t tmpCFGR2; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); __disable_irq(); /********** Save LPTIM Config *********/ /* Save LPTIM source clock */ switch ((uint32_t)LPTIMx) { case LPTIM1_BASE: tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); break; case LPTIM2_BASE: tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); break; case LPTIM3_BASE: case LPTIM4_BASE: case LPTIM5_BASE: tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE); break; default: break; } /* Save LPTIM configuration registers */ tmpIER = LPTIMx->IER; tmpCFGR = LPTIMx->CFGR; tmpCMP = LPTIMx->CMP; tmpARR = LPTIMx->ARR; tmpCFGR2 = LPTIMx->CFGR2; /************* Reset LPTIM ************/ (void)LL_LPTIM_DeInit(LPTIMx); /********* Restore LPTIM Config *******/ LL_RCC_GetSystemClocksFreq(&rcc_clock); if ((tmpCMP != 0UL) || (tmpARR != 0UL)) { /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)LPTIMx) { case LPTIM1_BASE: LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); break; case LPTIM2_BASE: LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4); break; case LPTIM3_BASE: case LPTIM4_BASE: case LPTIM5_BASE: LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4); break; default: break; } if (tmpCMP != 0UL) { /* Restore CMP and ARR registers (LPTIM should be enabled first) */ LPTIMx->CR |= LPTIM_CR_ENABLE; LPTIMx->CMP = tmpCMP; /* Polling on CMP write ok status after above restore operation */ do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } if (tmpARR != 0UL) { LPTIMx->CR |= LPTIM_CR_ENABLE; LPTIMx->ARR = tmpARR; LL_RCC_GetSystemClocksFreq(&rcc_clock); /* Polling on ARR write ok status after above restore operation */ do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } /* Restore LPTIM source kernel clock */ LL_RCC_SetLPTIMClockSource(tmpclksource); } /* Restore configuration registers (LPTIM should be disabled first) */ LPTIMx->CR &= ~(LPTIM_CR_ENABLE); LPTIMx->IER = tmpIER; LPTIMx->CFGR = tmpCFGR; LPTIMx->CFGR2 = tmpCFGR2; __enable_irq(); }