/* * ======== InterruptHost_intShmStub ======== */ Void InterruptHost_intShmStub(UArg arg) { InterruptHost_FxnTable *table; /* Process messages from the DSP */ if ((REG32(MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(DSP_TO_HOST)) && REG32(MAILBOX_STATUS(DSP_TO_HOST)) != 0) { table = &(InterruptHost_module->fxnTable[0]); (table->func)(table->arg); } /* Process messages from VIDEO */ if ((REG32(MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(VIDEO_TO_HOST)) && REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) != 0) { table = &(InterruptHost_module->fxnTable[1]); (table->func)(table->arg); } /* Process messages from VPSS */ if ((REG32(MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(VPSS_TO_HOST)) && REG32(MAILBOX_STATUS(VPSS_TO_HOST)) != 0) { table = &(InterruptHost_module->fxnTable[2]); (table->func)(table->arg); } }
/*! * ======== InterruptDucati_intShmMbxStub ======== */ Void InterruptDucati_intShmMbxStub(UArg arg) { InterruptDucati_FxnTable *table; if ((BIOS_smpEnabled) || (Core_getId() == 0)) { if ((REG32(MAILBOX_IRQENABLE_SET_VIDEO) & MAILBOX_REG_VAL(DSP_TO_VIDEO)) && REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) != 0) { /* DSP to VIDEO-M3 */ table = &(InterruptDucati_module->fxnTable[0]); (table->func)(table->arg); } if ((REG32(MAILBOX_IRQENABLE_SET_VIDEO) & MAILBOX_REG_VAL(HOST_TO_VIDEO)) && REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) != 0) { /* HOST to VIDEO-M3 */ table = &(InterruptDucati_module->fxnTable[1]); (table->func)(table->arg); } } else { if ((REG32(MAILBOX_IRQENABLE_SET_VPSS) & MAILBOX_REG_VAL(DSP_TO_VPSS)) && REG32(MAILBOX_STATUS(DSP_TO_VPSS)) != 0) { /* DSP to VPSS-M3 */ table = &(InterruptDucati_module->fxnTable[0]); (table->func)(table->arg); } if ((REG32(MAILBOX_IRQENABLE_SET_VPSS) & MAILBOX_REG_VAL(HOST_TO_VPSS)) && REG32(MAILBOX_STATUS(HOST_TO_VPSS)) != 0) { /* HOST to VPSS-M3 */ table = &(InterruptDucati_module->fxnTable[1]); (table->func)(table->arg); } } }
/*! * ======== InterruptDsp_intSend ======== * Send interrupt to the remote processor */ Void InterruptDsp_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; /* * Before writing to a mailbox, check whehter it already contains a message * If so, then don't write to the mailbox since we want one and only one * message per interrupt. Disable interrupts between reading * the MSGSTATUS_X register and writing to the mailbox to protect from * another thread doing an intSend at the same time */ if (remoteProcId == InterruptDsp_hostProcId) { /* Using mailbox 0 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_MPU)) == 0) { REG32(MAILBOX_MESSAGE(DSP_TO_MPU)) = arg; } Hwi_restore(key); } else if (remoteProcId == InterruptDsp_core0ProcId) { /* Using mailbox 1 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_M3)) == 0) { REG32(MAILBOX_MESSAGE(DSP_TO_M3)) = arg; } Hwi_restore(key); } else { Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal); } }
/* * ======== InterruptHost_intPost ======== */ Void InterruptHost_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (srcProcId == InterruptHost_vpssProcId) { /* VPSS-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VPSS_TO_HOST)) == 0) { REG32(MAILBOX_MESSAGE(VPSS_TO_HOST)) = arg; } Hwi_restore(key); } else if (srcProcId == InterruptHost_videoProcId) { /* VIDEO-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) == 0) { REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST)) = arg; } Hwi_restore(key); } else if (srcProcId == InterruptHost_dspProcId) { /* DSP */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_HOST)) == 0) { REG32(MAILBOX_MESSAGE(DSP_TO_HOST)) = arg; } Hwi_restore(key); } else { /* EVE */ key = Hwi_disable(); if (REG32(EVE_MAILBOX_STATUS(EVE_TO_HOST)) == 0) { REG32(EVE_MAILBOX_MESSAGE(EVE_TO_HOST)) = arg; } Hwi_restore(key); } }
/* * ======== InterruptEve_intShmStub ======== */ Void InterruptEve_intShmStub(UArg arg) { InterruptEve_FxnTable *table; /* Process messages from the HOST */ if ((REG32(MAILBOX_IRQENABLE_SET_EVE) & MAILBOX_REG_VAL(HOST_TO_EVE)) && REG32(MAILBOX_STATUS(HOST_TO_EVE)) != 0) { table = &(InterruptEve_module->fxnTable[0]); (table->func)(table->arg); } /* Process messages from VIDEO OR VPSS */ if ((REG32(MAILBOX_IRQENABLE_SET_EVE) & MAILBOX_REG_VAL(VIDEO_TO_EVE)) && REG32(MAILBOX_STATUS(VIDEO_TO_EVE)) != 0) { table = &(InterruptEve_module->fxnTable[1]); (table->func)(table->arg); } /* Process messages from DSP */ if ((REG32(MAILBOX_IRQENABLE_SET_EVE) & MAILBOX_REG_VAL(DSP_TO_EVE)) && REG32(MAILBOX_STATUS(DSP_TO_EVE)) != 0) { table = &(InterruptEve_module->fxnTable[2]); (table->func)(table->arg); } }
/*! * ======== InterruptDsp_intPost ======== */ Void InterruptDsp_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (srcProcId == InterruptDsp_vpssProcId) { key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VPSS_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(VPSS_TO_DSP)) = arg; } Hwi_restore(key); } else if (srcProcId == InterruptDsp_videoProcId) { key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VIDEO_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP)) = arg; } Hwi_restore(key); } else { /* hostProcId */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(HOST_TO_DSP)) = arg; } Hwi_restore(key); } }
/*! * ======== InterruptDucati_intSend ======== * Send interrupt to the remote processor */ Void InterruptDucati_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (remoteProcId == InterruptDucati_videoProcId || remoteProcId == InterruptDucati_vpssProcId) { if (!(BIOS_smpEnabled) && (Core_getId() == 1)) { /* VPSS-M3 to VIDEO-M3 */ REG16(INTERRUPT_VIDEO) |= 0x1; } else { /* VIDEO-M3 to VPSS-M3 */ REG16(INTERRUPT_VPSS) |= 0x1; } } else if (remoteProcId == InterruptDucati_dspProcId) { if (!(BIOS_smpEnabled) && (Core_getId() == 1)) { /* VPSS-M3 to DSP */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VPSS_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(VPSS_TO_DSP)) = arg; } Hwi_restore(key); } else { /* VIDEO-M3 to DSP */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VIDEO_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP)) = arg; } Hwi_restore(key); } } else { /* HOSTINT */ if (!(BIOS_smpEnabled) && (Core_getId() == 1)) { /* VPSS-M3 to HOST */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VPSS_TO_HOST)) == 0) { REG32(MAILBOX_MESSAGE(VPSS_TO_HOST)) = arg; } Hwi_restore(key); } else { /* VIDEO-M3 to HOST */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) == 0) { REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST)) = arg; } Hwi_restore(key); } } }
/*! * ======== InterruptDucati_intPost ======== * Simulate an interrupt from a remote processor */ Void InterruptDucati_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (srcProcId == InterruptDucati_videoProcId || srcProcId == InterruptDucati_vpssProcId) { if (!(BIOS_smpEnabled) && (Core_getId() == 1)) { /* VIDEO-M3 to VPSS-M3 */ REG16(INTERRUPT_VPSS) |= 0x1; } else { /* VPSS-M3 to VIDEO-M3 */ REG16(INTERRUPT_VIDEO) |= 0x1; } } else if (srcProcId == InterruptDucati_dspProcId) { if (!(BIOS_smpEnabled) && (Core_getId() == 1)) { /* DSP to VPSS-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_VPSS)) == 0) { REG32(MAILBOX_MESSAGE(DSP_TO_VPSS)) = arg; } Hwi_restore(key); } else { /* DSP to VIDEO-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) == 0) { REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO)) = arg; } Hwi_restore(key); } } else { /* HOSTINT */ if (!(BIOS_smpEnabled) && (Core_getId() == 1)) { /* HOST to VPSS-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_VPSS)) == 0) { REG32(MAILBOX_MESSAGE(HOST_TO_VPSS)) = arg; } Hwi_restore(key); } else { /* HOST to VIDEO-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) == 0) { REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO)) = arg; } Hwi_restore(key); } } }
/* * ======== InterruptHost_intSend ======== * Send interrupt to the remote processor */ Void InterruptHost_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; /* * Before writing to a mailbox, check whehter it already contains a message * If so, then don't write to the mailbox since we want one and only one * message per interrupt. Disable interrupts between reading * the MSGSTATUS_X register and writing to the mailbox to protect from * another thread doing an intSend at the same time * * Note regarding possible race condition between local 'intSend' and * remote 'intClear': * It is possible that we we read the MAILBOX_MSGSTATUS_X register during * the remote side's intClear. Therefore, we might choose _not_ to send * write to the mailbox even though the mailbox is about to be cleared a * few cycles later. In this case, the interrupt will be lost. * This is OK, however. intClear should always be called by the Notify * driver _before_ shared memory is read, so the event will be picked up * anyway by the previous interrupt that caused intClear to be called. */ if (remoteProcId == InterruptHost_dspProcId) { /* DSP */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(HOST_TO_DSP)) = arg; } Hwi_restore(key); } else if (remoteProcId == InterruptHost_videoProcId) { /* VIDEO-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) == 0) { REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO)) = arg; } Hwi_restore(key); } else if (remoteProcId == InterruptHost_vpssProcId) { /* VPSS-M3 */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_VPSS)) == 0) { REG32(MAILBOX_MESSAGE(HOST_TO_VPSS)) = arg; } Hwi_restore(key); } else { /* EVE */ key = Hwi_disable(); if (REG32(EVE_MAILBOX_STATUS(HOST_TO_EVE)) == 0) { REG32(EVE_MAILBOX_MESSAGE(HOST_TO_EVE)) = arg; } Hwi_restore(key); } }
/*! * ======== InterruptBenelli_intShmMbxStub ======== */ Void InterruptBenelli_intShmMbxStub(UArg arg) { UInt16 index; UInt16 selfIdx; UInt16 loopIdx; InterruptBenelli_FxnTable *table; selfIdx = MultiProc_self(); for (loopIdx = 0; loopIdx < MultiProc_getNumProcsInCluster(); loopIdx++) { if (loopIdx == selfIdx) { continue; } index = MBX_TABLE_IDX(loopIdx, selfIdx); if (((REG32(MAILBOX_STATUS(index)) != 0) && (REG32(MAILBOX_IRQENABLE_SET(index)) & MAILBOX_REG_VAL(SUBMBX_IDX(index))))) { table = &(InterruptBenelli_module->fxnTable[PROCID(loopIdx)]); (table->func)(table->arg); } } }
/*! * ======== InterruptDsp_intShmStub ======== */ Void InterruptDsp_intShmStub(UArg arg) { UInt16 index; UInt16 selfIdx; UInt16 loopIdx; InterruptDsp_FxnTable *table; selfIdx = MultiProc_self(); /* * Loop through each Sub-mailbox to determine which one generated * interrupt. */ for (loopIdx = 0; loopIdx < MultiProc_getNumProcsInCluster(); loopIdx++) { if (loopIdx == selfIdx) { continue; } index = MBX_TABLE_IDX(loopIdx, selfIdx); if ((REG32(MAILBOX_STATUS(index)) != 0) && (REG32(MAILBOX_IRQENABLE_SET_DSP(index)) & MAILBOX_REG_VAL(SUBMBX_IDX(index)))) { table = &(InterruptDsp_module->fxnTable[PROCID(loopIdx)]); (table->func)(table->arg); } } }
/*! * ======== InterruptDsp_intShmStub ======== */ Void InterruptDsp_intShmStub(UArg arg) { InterruptDsp_FxnTable *table; /* Process messages from HOST */ if ((REG32(MAILBOX_IRQENABLE_SET_DSP) & 0x40) && REG32(MAILBOX_STATUS(MPU_TO_DSP)) != 0) { table = &(InterruptDsp_module->fxnTable[0]); (table->func)(table->arg); } /* Process messages from CORE0 */ if ((REG32(MAILBOX_IRQENABLE_SET_DSP) & 0x10) && REG32(MAILBOX_STATUS(M3_TO_DSP)) != 0) { table = &(InterruptDsp_module->fxnTable[1]); (table->func)(table->arg); } }
/* * ======== InterruptEve_intPost ======== * Simulate an interrupt from a remote processor */ Void InterruptEve_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (srcProcId == InterruptEve_hostProcId) { /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(HOST_TO_EVE)) == 0) { /* write the mailbox message to arp32 */ REG32(MAILBOX_MESSAGE(HOST_TO_EVE)) = arg; } /* restore interrupts */ Hwi_restore(key); } else if ((srcProcId == InterruptEve_videoProcId) || (srcProcId == InterruptEve_vpssProcId)) { /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(VIDEO_TO_EVE)) == 0) { /* write the mailbox message to arp32 */ REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE)) = arg; } /* restore interrupts */ Hwi_restore(key); } else { /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_EVE)) == 0) { /* write the mailbox message to arp32 */ REG32(MAILBOX_MESSAGE(DSP_TO_EVE)) = arg; } /* restore interrupts */ Hwi_restore(key); } }
/* * ======== InterruptEve_intSend ======== * Send interrupt to the remote processor */ Void InterruptEve_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (remoteProcId == InterruptEve_hostProcId) { /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(EVE_TO_HOST)) == 0) { /* write the mailbox message to host */ REG32(MAILBOX_MESSAGE(EVE_TO_HOST)) = arg; } /* restore interrupts */ Hwi_restore(key); } else if ((remoteProcId == InterruptEve_videoProcId) || (remoteProcId == InterruptEve_vpssProcId)) { /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(EVE_TO_VIDEO)) == 0) { /* write the mailbox message to video-m3 */ REG32(MAILBOX_MESSAGE(EVE_TO_VIDEO)) = arg; } /* restore interrupts */ Hwi_restore(key); } else { /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(EVE_TO_DSP)) == 0) { /* write the mailbox message to dsp */ REG32(MAILBOX_MESSAGE(EVE_TO_DSP)) = arg; } /* restore interrupts */ key = Hwi_disable(); } }
/*! * ======== InterruptArp32_intShmStub ======== */ Void InterruptArp32_intShmStub(UArg arg) { InterruptArp32_FxnTable *table; if ((REG32(MAILBOX_IRQENABLE_SET(MBX_INTR_TO_ARP32)) & MAILBOX_REG_VAL(DSP_TO_ARP32)) && REG32(MAILBOX_STATUS(DSP_TO_ARP32)) != 0) { /* DSP to ARP32 */ /* call function with arg */ table = &(InterruptArp32_module->fxnTable); (table->func)(table->arg); } }
/*! * ======== InterruptDsp_intShmStub ======== */ Void InterruptDsp_intShmStub(UArg arg) { InterruptDsp_FxnTable *table; if (((REG32(MAILBOX_IRQENABLE_SET(MBX_INTR_TO_DSP)) & MAILBOX_REG_VAL(ARP32_TO_DSP)) && REG32(MAILBOX_STATUS(ARP32_TO_DSP))) != 0) { /* call function with arg */ table = &(InterruptDsp_module->fxnTable); (table->func)(table->arg); } }
/*! * ======== InterruptM3_intClear ======== * Clear interrupt and return payload */ UInt InterruptM3_intClear() { UInt arg = InterruptM3_INVALIDPAYLOAD; /* First check whether incoming mailbox has a message */ if (Core_getId() == 0) { /* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */ if (REG32(MAILBOX_STATUS(SYSM3_MBX)) == 0) { return (arg); } else { /* If there is a message, return the argument to the caller */ arg = REG32(MAILBOX_MESSAGE(SYSM3_MBX)); REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX); } } else { /* Clear the inter-M3 interrupt if necessary */ if ((REG16(INTERRUPT_CORE_1) & 0x1) == 0x1) { REG16(INTERRUPT_CORE_1) &= ~(0x1); } /* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */ if (REG32(MAILBOX_STATUS(APPM3_MBX)) == 0) { return (arg); } else { /* If there is a message, return the argument to the caller */ arg = REG32(MAILBOX_MESSAGE(APPM3_MBX)); REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(APPM3_MBX); if (REG32(MAILBOX_STATUS(APPM3_MBX)) != 0) { /* Trigger our own interrupt since another interrupt pending */ REG16(INTERRUPT_CORE_1) |= 0x1; } } } return (arg); }
Void task1(UArg arg0, UArg arg1) { sb_printf("\nWaiting for message.\n"); for (;;); #if 0 /* Waiting for a ping request from the remote (host) side */ while (!REG32(MAILBOX_STATUS(HOST_TO_SYSM3_MBX))); startExchange((Uint32)arg0); #endif }
/*! * ======== InterruptBenelli_intPost ======== * Simulate an interrupt from a remote processor */ Void InterruptBenelli_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; UInt16 index; index = MBX_TABLE_IDX(srcProcId, MultiProc_self()); key = Hwi_disable(); if (REG32(MAILBOX_STATUS(index)) == 0) { REG32(MAILBOX_MESSAGE(index)) = arg; } Hwi_restore(key); }
/*! * ======== InterruptDsp_intPost ======== * Send interrupt to the remote processor */ Void InterruptDsp_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; if (srcProcId == InterruptDsp_hostProcId) { key = Hwi_disable(); if (REG32(MAILBOX_STATUS(MPU_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(MPU_TO_DSP)) = arg; } Hwi_restore(key); } else if (srcProcId == InterruptDsp_core0ProcId) { key = Hwi_disable(); if (REG32(MAILBOX_STATUS(M3_TO_DSP)) == 0) { REG32(MAILBOX_MESSAGE(M3_TO_DSP)) = arg; } Hwi_restore(key); } else { Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal); } }
/*! * ======== InterruptArp32_intSend ======== * Send interrupt to the remote processor */ Void InterruptArp32_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(ARP32_TO_DSP)) == 0) { /* write the mailbox message to dsp */ REG32(MAILBOX_MESSAGE(ARP32_TO_DSP)) = arg; } /* restore interrupts */ Hwi_restore(key); }
/*! * ======== InterruptArp32_intPost ======== * Simulate an interrupt from a remote processor */ Void InterruptArp32_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(DSP_TO_ARP32)) == 0) { /* write the mailbox message to arp32 */ REG32(MAILBOX_MESSAGE(DSP_TO_ARP32)) = arg; } /* restore interrupts */ Hwi_restore(key); }
/*! * ======== InterruptIpu_intClear ======== * Clear interrupt and return payload */ UInt InterruptIpu_intClear() { UInt arg = INVALIDPAYLOAD; /* If FIFO is empty, return INVALIDPAYLOAD */ if (REG32(MAILBOX_STATUS(HOST_TO_SYSM3_MBX)) == 0) { return (arg); } else { /* If there is a message, return the argument to the caller */ arg = REG32(MAILBOX_MESSAGE(HOST_TO_SYSM3_MBX)); REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(HOST_TO_SYSM3_MBX); } return (arg); }
/*! * ======== InterruptArp32_intPost ======== * Simulate an interrupt from a remote processor */ Void InterruptArp32_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo, UArg arg) { UInt key; UInt16 index; index = MBX_TABLE_IDX(srcProcId, MultiProc_self()); /* disable interrupts */ key = Hwi_disable(); if (REG32(MAILBOX_STATUS(index)) == 0) { /* write the mailbox message to arp32 */ REG32(MAILBOX_MESSAGE(index)) = arg; } /* restore interrupts */ Hwi_restore(key); }