void DWire::begin( ) { // Initialising the given module as a master busRole = BUS_ROLE_MASTER; slaveAddress = 0; _initMain( ); // calculate the number of iterations of a loop to generate // a delay based on clock speed // this is needed to handle NACKs in a way that is independent // of CPU speed and OS (Energia or not) delayCycles = MAP_CS_getMCLK( ) * 12 / 7905857; /* Set the EUSCI configuration */ config.selectClockSource = EUSCI_B_I2C_CLOCKSOURCE_SMCLK; // SMCLK Clock Source config.i2cClk = MAP_CS_getSMCLK( ); // Get the SMCLK clock frequency config.byteCounterThreshold = 0; // No byte counter threshold config.autoSTOPGeneration = EUSCI_B_I2C_NO_AUTO_STOP; // No Autostop if (mode == FAST) { config.dataRate = EUSCI_B_I2C_SET_DATA_RATE_400KBPS; _initMaster( &config ); // accommodate a delay of at least ~30us (~68us measured) delayCycles = delayCycles * 4; } else if(mode == FASTPLUS) { config.dataRate = EUSCI_B_I2C_SET_DATA_RATE_1MBPS; _initMaster( &config ); // accommodate a delay of ~12us (~16us measured) } else { config.dataRate = EUSCI_B_I2C_SET_DATA_RATE_100KBPS; _initMaster( &config ); // accommodate a delay of at least ~120us (~130 us measured) delayCycles = delayCycles * 10; } }
#ifdef USING_EUSCI_B3 uint8_t EUSCIB3_txBuffer[TX_BUFFER_SIZE]; uint8_t EUSCIB3_txBufferIndex = 0; uint8_t EUSCIB3_txBufferSize = 0; uint8_t EUSCIB3_rxBuffer[RX_BUFFER_SIZE]; uint8_t EUSCIB3_rxBufferIndex = 0; uint8_t EUSCIB3_rxBufferSize = 0; #endif // The default eUSCI settings const eUSCI_I2C_MasterConfig i2cConfig = { EUSCI_B_I2C_CLOCKSOURCE_SMCLK, // SMCLK Clock Source MAP_CS_getSMCLK(), // Get the SMCLK clock frequency EUSCI_B_I2C_SET_DATA_RATE_400KBPS, // Desired I2C Clock of 400khz // TODO make configurable 0, // No byte counter threshold EUSCI_B_I2C_NO_AUTO_STOP // No Autostop }; /**** CONSTRUCTORS ****/ DWire::DWire( void ) { } DWire::~DWire() { // Deregister from the moduleMap unregisterModule(this); }