//*****************************************************************************
//
//! \InterruptTestTerm
//! Performs termination processing.
//! This function is called once the test completes to tidy up as required.
//!
//! \param None.
//!
//! \return None.
//
//*****************************************************************************
static void
InterruptTestTerm(void)
{
//
// Unhook our interrupt handlers if they are still hooked.
//
TimerIntUnregister(TIMERA0_BASE, TIMER_A);
TimerIntUnregister(TIMERA1_BASE, TIMER_A);
TimerIntUnregister(TIMERA2_BASE, TIMER_A);
//
// Restore the original timer interrupt priorities and priority group
// settings.
//
MAP_IntPriorityGroupingSet(g_lPriorityGrouping);
MAP_IntPrioritySet(INT_TIMERA0A, (unsigned char)g_ulTimer0APriority);
MAP_IntPrioritySet(INT_TIMERA1A, (unsigned char)g_ulTimer1APriority);
//
// Reset and Disable the timer blocks
//
MAP_PRCMPeripheralReset(PRCM_TIMERA0);
MAP_PRCMPeripheralReset(PRCM_TIMERA1);
MAP_PRCMPeripheralReset(PRCM_TIMERA2);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA0, PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA1, PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralClkDisable(PRCM_TIMERA2, PRCM_RUN_MODE_CLK);
}
int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) //do not know what to do with pValue
{
if(InterruptHdl == NULL)
{
//De-register Interprocessor communication interrupt between App and NWP
#ifdef SL_PLATFORM_MULTI_THREADED
osi_InterruptDeRegister(INT_NWPIC);
#else
MAP_IntDisable(INT_NWPIC);
MAP_IntUnregister(INT_NWPIC);
MAP_IntPendClear(INT_NWPIC);
#endif
}
else
{
#ifdef SL_PLATFORM_MULTI_THREADED
MAP_IntPendClear(INT_NWPIC);
osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)InterruptHdl,
INT_PRIORITY_LVL_1);
#else
MAP_IntRegister(INT_NWPIC, InterruptHdl);
MAP_IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
MAP_IntPendClear(INT_NWPIC);
MAP_IntEnable(INT_NWPIC);
#endif
}
return 0;
}
void CANController::enableInterrupts(uint32_t interruptFlags)
{
unsigned long INT;
switch (_channel) {
#ifdef HAS_CAN_CHANNEL_0
case CAN::channel_0:
INT = INT_CAN0;
break;
#endif
#ifdef HAS_CAN_CHANNEL_1
case CAN::channel_1:
INT = INT_CAN1;
break;
#endif
#ifdef HAS_CAN_CHANNEL_2
case CAN::channel_2:
INT = INT_CAN2;
break;
#endif
default:
while(1);
break;
}
MAP_CANIntEnable(_base, interruptFlags);
MAP_IntPrioritySet(INT, configDEFAULT_SYSCALL_INTERRUPT_PRIORITY);
IntEnable(INT);
}
bool mgos_uart_hal_init(struct mgos_uart_state *us) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
uint32_t periph, int_no;
void (*int_handler)();
/* TODO(rojer): Configurable pin mappings? */
if (us->uart_no == 0) {
periph = PRCM_UARTA0;
int_no = INT_UARTA0;
int_handler = u0_int;
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
} else if (us->uart_no == 1) {
periph = PRCM_UARTA1;
int_no = INT_UARTA1;
int_handler = u1_int;
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
} else {
return false;
}
struct cc32xx_uart_state *ds =
(struct cc32xx_uart_state *) calloc(1, sizeof(*ds));
ds->base = base;
cs_rbuf_init(&ds->isr_rx_buf, CC32xx_UART_ISR_RX_BUF_SIZE);
us->dev_data = ds;
MAP_PRCMPeripheralClkEnable(periph, PRCM_RUN_MODE_CLK);
MAP_UARTIntDisable(base, ~0); /* Start with ints disabled. */
MAP_IntRegister(int_no, int_handler);
MAP_IntPrioritySet(int_no, INT_PRIORITY_LVL_1);
MAP_IntEnable(int_no);
return true;
}
void timerInit()
{
#ifdef TARGET_IS_BLIZZARD_RB1
//
// Run at system clock at 80MHz
//
MAP_SysCtlClockSet(SYSCTL_SYSDIV_2_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|
SYSCTL_OSC_MAIN);
#else
//
// Run at system clock at 120MHz
//
MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ|SYSCTL_OSC_MAIN|SYSCTL_USE_PLL|SYSCTL_CFG_VCO_480), F_CPU);
#endif
//
// SysTick is used for delay() and delayMicroseconds()
//
MAP_SysTickPeriodSet(F_CPU / SYSTICKHZ);
MAP_SysTickEnable();
MAP_IntPrioritySet(FAULT_SYSTICK, SYSTICK_INT_PRIORITY);
MAP_SysTickIntEnable();
MAP_IntMasterEnable();
// PIOSC is used during Deep Sleep mode for wakeup
MAP_SysCtlPIOSCCalibrate(SYSCTL_PIOSC_CAL_FACT); // Factory-supplied calibration used
}
STATIC void pin_extint_register(pin_obj_t *self, uint32_t intmode, uint32_t priority) {
void *handler;
uint32_t intnum;
// configure the interrupt type
MAP_GPIOIntTypeSet(self->port, self->bit, intmode);
switch (self->port) {
case GPIOA0_BASE:
handler = GPIOA0IntHandler;
intnum = INT_GPIOA0;
break;
case GPIOA1_BASE:
handler = GPIOA1IntHandler;
intnum = INT_GPIOA1;
break;
case GPIOA2_BASE:
handler = GPIOA2IntHandler;
intnum = INT_GPIOA2;
break;
case GPIOA3_BASE:
default:
handler = GPIOA3IntHandler;
intnum = INT_GPIOA3;
break;
}
MAP_GPIOIntRegister(self->port, handler);
// set the interrupt to the lowest priority, to make sure that
// no other ISRs will be preemted by this one
MAP_IntPrioritySet(intnum, priority);
}
STATIC void pin_extint_register(pin_obj_t *self, uint32_t intmode, uint32_t priority) {
//void *handler;
uint32_t intnum;
// configure the interrupt type
MAP_GPIOIntTypeSet(self->port, self->bit, intmode);
switch (self->port) {
case GPIO_PORTA_BASE:
intnum = INT_GPIOA_TM4C123;
break;
case GPIO_PORTB_BASE:
intnum = INT_GPIOB_TM4C123;
break;
case GPIO_PORTC_BASE:
intnum = INT_GPIOC_TM4C123;
break;
case GPIO_PORTD_BASE:
intnum = INT_GPIOD_TM4C123;
case GPIO_PORTE_BASE:
intnum = INT_GPIOE_TM4C123;
case GPIO_PORTF_BASE:
default:
intnum = INT_GPIOF_TM4C123;
break;
}
// set the interrupt to the lowest priority, to make sure that
// no other ISRs will be preemted by this one
MAP_IntPrioritySet(intnum, priority);
}
/*!
\brief This function registers an interrupt in NVIC table
The sync object is used for synchronization between different thread or ISR and
a thread.
\param iIntrNum - Interrupt number to register
\param pEntry - Pointer to the interrupt handler
\param ucPriority - priority of the interrupt
\return upon successful creation the function should return 0
Otherwise, a negative value indicating the error code shall be returned
\note
\warning
*/
OsiReturnVal_e osi_InterruptRegister(int iIntrNum,P_OSI_INTR_ENTRY pEntry,unsigned char ucPriority)
{
MAP_IntRegister(iIntrNum,(void(*)(void))pEntry);
MAP_IntPrioritySet(iIntrNum, ucPriority);
MAP_IntEnable(iIntrNum);
return OSI_OK;
}
//****************************************************************************
//
//! Configures the GPIO selected as input to generate interrupt on activity
//!
//! \param uiGPIOPort is the GPIO port address
//! \param ucGPIOPin is the GPIO pin of the specified port
//! \param uiIntType is the type of the interrupt (refer gpio.h)
//! \param pfnIntHandler is the interrupt handler to register
//!
//! This function
//! 1. Sets GPIO interrupt type
//! 2. Registers Interrupt handler
//! 3. Enables Interrupt
//!
//! \return None
//
//****************************************************************************
void
GPIO_IF_ConfigureNIntEnable(unsigned int uiGPIOPort,
unsigned char ucGPIOPin,
unsigned int uiIntType,
void (*pfnIntHandler)(void))
{
//
// Set GPIO interrupt type
//
MAP_GPIOIntTypeSet(uiGPIOPort,ucGPIOPin,uiIntType);
//
// Register Interrupt handler
//
#if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED)
// USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking)
// USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking)
// SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink)
osi_InterruptRegister(GetPeripheralIntNum(uiGPIOPort),
pfnIntHandler, INT_PRIORITY_LVL_1);
#else
MAP_IntPrioritySet(GetPeripheralIntNum(uiGPIOPort), INT_PRIORITY_LVL_1);
MAP_GPIOIntRegister(uiGPIOPort,pfnIntHandler);
#endif
//
// Enable Interrupt
//
MAP_GPIOIntClear(uiGPIOPort,ucGPIOPin);
MAP_GPIOIntEnable(uiGPIOPort,ucGPIOPin);
}
//*****************************************************************************
//
//! Initialize the DMA controller
//!
//! \param None
//!
//! This function initializes
//! 1. Initializes the McASP module
//!
//! \return None.
//
//*****************************************************************************
void UDMAInit()
{
unsigned int uiLoopCnt;
//
// Enable McASP at the PRCM module
//
MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
MAP_PRCMPeripheralReset(PRCM_UDMA);
//
// Register interrupt handlers
//
#if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED)
// USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking)
// USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking)
// SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink)
osi_InterruptRegister(INT_UDMA, DmaSwIntHandler, INT_PRIORITY_LVL_1);
osi_InterruptRegister(INT_UDMAERR, DmaErrorIntHandler, INT_PRIORITY_LVL_1);
#else
MAP_IntPrioritySet(INT_UDMA, INT_PRIORITY_LVL_1);
MAP_uDMAIntRegister(UDMA_INT_SW, DmaSwIntHandler);
MAP_IntPrioritySet(INT_UDMAERR, INT_PRIORITY_LVL_1);
MAP_uDMAIntRegister(UDMA_INT_ERR, DmaErrorIntHandler);
#endif
//
// Enable uDMA using master enable
//
MAP_uDMAEnable();
//
// Set Control Table
//
memset(gpCtlTbl,0,sizeof(tDMAControlTable)*CTL_TBL_SIZE);
MAP_uDMAControlBaseSet(gpCtlTbl);
//
// Reset App Callbacks
//
for(uiLoopCnt = 0; uiLoopCnt < MAX_NUM_CH; uiLoopCnt++)
{
gfpAppCallbackHndl[uiLoopCnt] = NULL;
}
}
// assumes init parameters have been set up correctly
bool uart_init2(pyb_uart_obj_t *self) {
uint uartPerh;
switch (self->uart_id) {
case PYB_UART_0:
self->reg = UARTA0_BASE;
uartPerh = PRCM_UARTA0;
MAP_UARTIntRegister(UARTA0_BASE, UART0IntHandler);
MAP_IntPrioritySet(INT_UARTA0, INT_PRIORITY_LVL_3);
break;
case PYB_UART_1:
self->reg = UARTA1_BASE;
uartPerh = PRCM_UARTA1;
MAP_UARTIntRegister(UARTA1_BASE, UART1IntHandler);
MAP_IntPrioritySet(INT_UARTA1, INT_PRIORITY_LVL_3);
break;
default:
return false;
}
// Enable the peripheral clock
MAP_PRCMPeripheralClkEnable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// Reset the uart
MAP_PRCMPeripheralReset(uartPerh);
// Initialize the UART
MAP_UARTConfigSetExpClk(self->reg, MAP_PRCMPeripheralClockGet(uartPerh),
self->baudrate, self->config);
// Enbale the FIFO
MAP_UARTFIFOEnable(self->reg);
// Configure the FIFO interrupt levels
MAP_UARTFIFOLevelSet(self->reg, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
// Configure the flow control mode
UARTFlowControlSet(self->reg, self->flowcontrol);
// Enable the RX and RX timeout interrupts
MAP_UARTIntEnable(self->reg, UART_INT_RX | UART_INT_RT);
self->enabled = true;
return true;
}
USBController::USBController(controller_num_t num) :
_num(num), _mode(mode_none)
{
switch (num) {
case controller_0:
_base = USB0_BASE;
_int = INT_USB0;
_periph = SYSCTL_PERIPH_USB0;
_intHandler = USB0DeviceIntHandler;
_otgIntHandler = USB0OTGModeIntHandler;
break;
default:
while(1);
}
MAP_SysCtlPeripheralEnable(_periph);
MAP_IntPrioritySet(INT_USB0, configDEFAULT_SYSCALL_INTERRUPT_PRIORITY);
}
//*****************************************************************************
//
//! setting up the timer
//!
//! \param ulBase is the base address for the timer.
//! \param ulTimer selects between the TIMER_A or TIMER_B or TIMER_BOTH.
//! \param TimerBaseIntHandler is the pointer to the function that handles the
//! interrupt for the Timer
//!
//! This function
//! 1. Register the function handler for the timer interrupt.
//! 2. enables the timer interrupt.
//!
//! \return none
//
//*****************************************************************************
void Timer_IF_IntSetup(unsigned long ulBase, unsigned long ulTimer,
void (*TimerBaseIntHandler)(void))
{
//
// Setup the interrupts for the timer timeouts.
//
#if defined(USE_TIRTOS) || defined(USE_FREERTOS) || defined(SL_PLATFORM_MULTI_THREADED)
// USE_TIRTOS: if app uses TI-RTOS (either networking/non-networking)
// USE_FREERTOS: if app uses Free-RTOS (either networking/non-networking)
// SL_PLATFORM_MULTI_THREADED: if app uses any OS + networking(simplelink)
if(ulTimer == TIMER_BOTH)
{
osi_InterruptRegister(GetPeripheralIntNum(ulBase, TIMER_A),
TimerBaseIntHandler, INT_PRIORITY_LVL_1);
osi_InterruptRegister(GetPeripheralIntNum(ulBase, TIMER_B),
TimerBaseIntHandler, INT_PRIORITY_LVL_1);
}
else
{
osi_InterruptRegister(GetPeripheralIntNum(ulBase, ulTimer),
TimerBaseIntHandler, INT_PRIORITY_LVL_1);
}
#else
MAP_IntPrioritySet(GetPeripheralIntNum(ulBase, ulTimer), INT_PRIORITY_LVL_1);
MAP_TimerIntRegister(ulBase, ulTimer, TimerBaseIntHandler);
#endif
if(ulTimer == TIMER_BOTH)
{
MAP_TimerIntEnable(ulBase, TIMER_TIMA_TIMEOUT|TIMER_TIMB_TIMEOUT);
}
else
{
MAP_TimerIntEnable(ulBase, ((ulTimer == TIMER_A) ? TIMER_TIMA_TIMEOUT :
TIMER_TIMB_TIMEOUT));
}
}
Thread::Error Watchdog::start() {
MAP_PRCMPeripheralClkEnable(PRCM_WDT, PRCM_RUN_MODE_CLK);
MAP_WatchdogUnlock(WDT_BASE);
MAP_WatchdogStallEnable(WDT_BASE);
MAP_IntPrioritySet(INT_WDT, INT_PRIORITY_LVL_1);
MAP_WatchdogIntRegister(WDT_BASE, isr);
MAP_WatchdogReloadSet(WDT_BASE, 240000000UL);
MAP_WatchdogEnable(WDT_BASE);
Thread::Error err = Thread::start();
if (err != Thread::kOK)
stop();
return err;
}
void InitUartInterface(uint32_t sys_clock)
{
uart_rx_read_index = 0;
uart_rx_write_index = 0;
const uint32_t dma_rx_primary = UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT;
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART1);
//921600
//460800
uint32_t uart_config = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE;
UARTConfigSetExpClk(UART1_BASE, sys_clock, 921600, uart_config);
GPIOPinConfigure(GPIO_PB0_U1RX);
GPIOPinConfigure(GPIO_PB1_U1TX);
GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
UARTEnable(UART1_BASE);
//UARTDMAEnable(UART1_BASE, UART_DMA_RX | UART_DMA_TX);
UARTDMAEnable(UART1_BASE, UART_DMA_RX);
// Put the attributes in a known state for the uDMA UART1RX channel. These
// should already be disabled by default.
uint32_t dma_config = UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK;
uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1RX, dma_config);
uint32_t dma_control = UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4;
uDMAChannelControlSet(dma_rx_primary, dma_control);
uDMAChannelTransferSet(dma_rx_primary, UDMA_MODE_BASIC, (void *)(UART1_BASE + UART_O_DR), &uart_rx_buf[uart_rx_write_index], UART_RX_BLOCK_SIZE);
// Put the attributes in a known state for the uDMA UART1TX channel. These
// should already be disabled by default.
// uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1TX,
// UDMA_ATTR_ALTSELECT |
// UDMA_ATTR_HIGH_PRIORITY |
// UDMA_ATTR_REQMASK);
// Set the USEBURST attribute for the uDMA UART TX channel. This will
// force the controller to always use a burst when transferring data from
// the TX buffer to the UART. This is somewhat more effecient bus usage
// than the default which allows single or burst transfers.
//uDMAChannelAttributeEnable(UDMA_CHANNEL_UART1TX, UDMA_ATTR_USEBURST);
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
// uDMAChannelControlSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT,
// UDMA_SIZE_8 | UDMA_SRC_INC_8 |
// UDMA_DST_INC_NONE |
// UDMA_ARB_4);
// Set up the transfer parameters for the uDMA UART TX channel. This will
// configure the transfer source and destination and the transfer size.
// Basic mode is used because the peripheral is making the uDMA transfer
// request. The source is the TX buffer and the destination is the UART
// data register.
// uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT,
// UDMA_MODE_BASIC, g_ui8TxBuf,
// (void *)(UART1_BASE + UART_O_DR),
// sizeof(g_ui8TxBuf));
// Now both the uDMA UART TX and RX channels are primed to start a
// transfer. As soon as the channels are enabled, the peripheral will
// issue a transfer request and the data transfers will begin.
uDMAChannelEnable(UDMA_CHANNEL_UART1RX);
//uDMAChannelEnable(UDMA_CHANNEL_UART1TX);
// Enable the UART DMA TX/RX interrupts.
//UARTIntEnable(UART1_BASE, UART_INT_DMATX | UART_INT_DMATX);
UARTIntEnable(UART1_BASE, UART_INT_DMARX);
IntEnable(INT_UART1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
MAP_TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);
MAP_TimerLoadSet(TIMER0_BASE, TIMER_A, sys_clock / 2000);
MAP_IntEnable(INT_TIMER0A);
MAP_TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
MAP_TimerEnable(TIMER0_BASE, TIMER_A);
MAP_IntPrioritySet(INT_TIMER0A, 0xC0);
}
/* success. */
int BTPSAPI HCITR_COMOpen(HCI_COMMDriverInformation_t *COMMDriverInformation, HCITR_COMDataCallback_t COMDataCallback, unsigned long CallbackParameter)
{
int ret_val;
/* First, make sure that the port is not already open and make sure */
/* that valid COMM Driver Information was specified. */
if((!HCITransportOpen) && (COMMDriverInformation) && (COMDataCallback))
{
/* Initialize the return value for success. */
ret_val = TRANSPORT_ID;
/* Note the COM Callback information. */
_COMDataCallback = COMDataCallback;
_COMCallbackParameter = CallbackParameter;
/* Initialize the UART Context Structure. */
BTPS_MemInitialize(&UartContext, 0, sizeof(UartContext_t));
UartContext.Base = HCI_UART_BASE;
UartContext.IntBase = HCI_UART_INT;
UartContext.ID = 1;
UartContext.FlowInfo = UART_CONTEXT_FLAG_FLOW_CONTROL_ENABLED;
UartContext.XOnLimit = DEFAULT_XON_LIMIT;
UartContext.XOffLimit = DEFAULT_XOFF_LIMIT;
UartContext.RxBufferSize = DEFAULT_INPUT_BUFFER_SIZE;
UartContext.RxBytesFree = DEFAULT_INPUT_BUFFER_SIZE;
UartContext.TxBufferSize = DEFAULT_OUTPUT_BUFFER_SIZE;
UartContext.TxBytesFree = DEFAULT_OUTPUT_BUFFER_SIZE;
/* Flag that the Rx Thread should not delete itself. */
RxThreadDeleted = FALSE;
/* Check to see if this is the first time that the port has been */
/* opened. */
if(!Handle)
{
/* Configure the UART module and the GPIO pins used by the */
/* UART. */
MAP_SysCtlPeripheralEnable(HCI_UART_GPIO_PERIPH);
MAP_SysCtlPeripheralEnable(HCI_UART_RTS_GPIO_PERIPH);
MAP_SysCtlPeripheralEnable(HCI_UART_CTS_GPIO_PERIPH);
MAP_SysCtlPeripheralEnable(HCI_UART_PERIPH);
MAP_GPIOPinConfigure(HCI_PIN_CONFIGURE_UART_RX);
MAP_GPIOPinConfigure(HCI_PIN_CONFIGURE_UART_TX);
MAP_GPIOPinConfigure(HCI_PIN_CONFIGURE_UART_RTS);
MAP_GPIOPinConfigure(HCI_PIN_CONFIGURE_UART_CTS);
MAP_GPIOPinTypeUART(HCI_UART_GPIO_BASE, HCI_UART_PIN_RX | HCI_UART_PIN_TX);
MAP_GPIOPinTypeUART(HCI_UART_RTS_GPIO_BASE, HCI_UART_PIN_RTS);
MAP_GPIOPinTypeUART(HCI_UART_CTS_GPIO_BASE, HCI_UART_PIN_CTS);
UARTFlowControlSet(UartContext.Base, UART_FLOWCONTROL_RX | UART_FLOWCONTROL_TX);
/* Create an Event that will be used to signal that data has */
/* arrived. */
RxDataEvent = BTPS_CreateEvent(FALSE);
if(RxDataEvent)
{
/* Create a thread that will process the received data. */
Handle = BTPS_CreateThread(RxThread, 1600, NULL);
if(!Handle)
{
BTPS_CloseEvent(RxDataEvent);
ret_val = HCITR_ERROR_UNABLE_TO_OPEN_TRANSPORT;
}
}
else
ret_val = HCITR_ERROR_UNABLE_TO_OPEN_TRANSPORT;
}
/* If there was no error, then continue to setup the port. */
if(ret_val != HCITR_ERROR_UNABLE_TO_OPEN_TRANSPORT)
{
/* Configure UART Baud Rate and Interrupts. */
MAP_UARTConfigSetExpClk(UartContext.Base, MAP_SysCtlClockGet(), COMMDriverInformation->BaudRate, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
/* SafeRTOS requires RTOS-aware int handlers to be priority */
/* value 5 or greater */
MAP_IntPrioritySet(UartContext.IntBase, 6 << 5);
MAP_IntEnable(UartContext.IntBase);
MAP_UARTIntEnable(UartContext.Base, UART_INT_RX | UART_INT_RT);
UartContext.Flags |= UART_CONTEXT_FLAG_RX_FLOW_ENABLED;
/* Clear any data that is in the Buffer. */
FlushRxFIFO(UartContext.Base);
/* Bring the Bluetooth Device out of Reset. */
MAP_GPIOPinWrite(HCI_RESET_BASE, HCI_RESET_PIN, HCI_RESET_PIN);
/* Check to see if we need to delay after opening the COM Port.*/
if(COMMDriverInformation->InitializationDelay)
BTPS_Delay(COMMDriverInformation->InitializationDelay);
/* Flag that the HCI Transport is open. */
HCITransportOpen = 1;
}
}
else
ret_val = HCITR_ERROR_UNABLE_TO_OPEN_TRANSPORT;
return(ret_val);
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
unsigned long ulBase;
unsigned long ulSpiBitRate;
tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR);
//NWP master interface
ulBase = LSPI_BASE;
//Enable MCSPIA2
MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);
//Disable Chip Select
MAP_SPICSDisable(ulBase);
//Disable SPI Channel
MAP_SPIDisable(ulBase);
// Reset SPI
MAP_SPIReset(ulBase);
//
// Configure SPI interface
//
if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 )
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32)
{
ulSpiBitRate = SPI_RATE_13M;
}
else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33)
{
ulSpiBitRate = SPI_RATE_20M;
}
MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS |
SPI_4PIN_MODE |
SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_32));
if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA))
{
g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
}
else
{
g_ucDMAEnabled = 0;
}
#ifdef SL_CPU_MODE
g_ucDMAEnabled = 0;
#endif
if(g_ucDMAEnabled)
{
memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));
// Set DMA channel
cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);
cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);
MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO);
MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO);
MAP_SPIDmaEnable(ulBase,SPI_RX_DMA);
MAP_SPIDmaEnable(ulBase,SPI_TX_DMA);
MAP_SPIFIFOLevelSet(ulBase,1,1);
#if defined(SL_PLATFORM_MULTI_THREADED)
osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);
#else
MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);
MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);
MAP_IntEnable(INT_LSPI);
MAP_SPIIntEnable(ulBase,SPI_INT_EOW);
g_cDummy = 0x0;
#endif
}
MAP_SPIEnable(ulBase);
g_SpiFd = 1;
return g_SpiFd;
}
//*****************************************************************************
//
//! \PerformIntTest
//!
//! Performs the repeated steps in running each test scenario.
//!
//! \param ucPriorityA0 is the interrupt priority to be used for Timer A0
//! \param ucPriorityA1 is the interrupt priority to be used for Timer A1
//! \param ucPriorityA2 is the interrupt priority to be used for Timer A2
//!
//! This function performs all the steps which are common to each test scenario
//! inside function InterruptTest.
//!
//! \return None.
//
//*****************************************************************************
tBoolean
PerformIntTest(unsigned long ulPriBits, unsigned char ucPriorityA0,
unsigned char ucPriorityA1,unsigned char ucPriorityA2)
{
tBoolean bRetcode;
unsigned long ulStatus;
//
// Set the appropriate interrupt priorities.
//
MAP_IntPriorityGroupingSet(ulPriBits);
MAP_IntPrioritySet(INT_TIMERA0A, ucPriorityA0);
MAP_IntPrioritySet(INT_TIMERA1A, ucPriorityA1);
MAP_IntPrioritySet(INT_TIMERA2A, ucPriorityA2);
//
// Clear any pending timer interrupts
//
ulStatus = MAP_TimerIntStatus(TIMERA0_BASE, false);
MAP_TimerIntClear(TIMERA0_BASE, ulStatus);
ulStatus = MAP_TimerIntStatus(TIMERA1_BASE, false);
MAP_TimerIntClear(TIMERA1_BASE, ulStatus);
ulStatus = MAP_TimerIntStatus(TIMERA2_BASE, false);
MAP_TimerIntClear(TIMERA2_BASE, ulStatus);
//
// Clear all the counters and flags used by the interrupt handlers.
//
g_ulA0IntCount = 0;
g_ulA1IntCount = 0;
g_ulA2IntCount=0;
g_bA1CountChanged = false;
//
// Enable three timer interrupts
//
MAP_TimerIntEnable(TIMERA0_BASE, TIMER_TIMA_TIMEOUT);
MAP_TimerIntEnable(TIMERA1_BASE, TIMER_TIMA_TIMEOUT);
MAP_TimerIntEnable(TIMERA2_BASE, TIMER_TIMA_TIMEOUT);
//
// Enable Timer A0
//
MAP_TimerEnable(TIMERA0_BASE, TIMER_A);
//
// Wait for Timer 0/A to fire.
//
bRetcode = UTUtilsWaitForCount(&g_ulA0IntCount, 1,
((SLOW_TIMER_DELAY_uS*3)/1000));
//
// Stop All timers and disable their interrupts
//
MAP_TimerDisable(TIMERA2_BASE, TIMER_A);
MAP_TimerDisable(TIMERA1_BASE, TIMER_A);
MAP_TimerDisable(TIMERA0_BASE, TIMER_A);
MAP_TimerIntDisable(TIMERA2_BASE, TIMER_TIMA_TIMEOUT);
MAP_TimerIntDisable(TIMERA1_BASE, TIMER_TIMA_TIMEOUT);
MAP_TimerIntDisable(TIMERA0_BASE, TIMER_TIMA_TIMEOUT);
return(bRetcode);
}
int main()
{
//
// Make sure the main oscillator is enabled because this is required by
// the PHY. The system must have a 25MHz crystal attached to the OSC
// pins. The SYSCTL_MOSC_HIGHFREQ parameter is used when the crystal
// frequency is 10MHz or higher.
//
SysCtlMOSCConfigSet(SYSCTL_MOSC_HIGHFREQ);
//
// Run from the PLL at 120 MHz.
//
g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);
// Configure the device pins.
//
PinoutSet(true, false);
//
// Configure UART.
//
//UARTStdioConfig(0, 115200, g_ui32SysClock);
//
// Clear the terminal and print banner.
//
//UARTprintf("\033[2J\033[H");
//UARTprintf("Ethernet lwIP example\n\n");
//
// Configure Port N1 for as an output for the animation LED.
//
MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1);
MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0);
MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1);
//
// Initialize LED to OFF (0)
//
MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1, ~GPIO_PIN_1);
MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, ~GPIO_PIN_0);
MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, ~GPIO_PIN_1);
//
// Configure SysTick for a periodic interrupt.
//
MAP_SysTickPeriodSet(g_ui32SysClock / SYSTICKHZ);
MAP_SysTickEnable();
MAP_SysTickIntEnable();
// Init Onion Client
client = new OnionClient("o8Ik6DuC","NfyGRECh3WSZw9xn");
client->registerFunction("/on",ledOn,0,0);
client->registerFunction("/off",ledOff,0,0);
char *params[1] = {"data"};
client->registerFunction("/pubTest",pubTest,params,1);
client->init(g_ui32SysClock);
//
// Setup Onion Client
//
//httpd_init();
//client->begin();
//
// Set the interrupt priorities. We set the SysTick interrupt to a higher
// priority than the Ethernet interrupt to ensure that the file system
// tick is processed if SysTick occurs while the Ethernet handler is being
// processed. This is very likely since all the TCP/IP and HTTP work is
// done in the context of the Ethernet interrupt.
//
MAP_IntPrioritySet(INT_EMAC0, ETHERNET_INT_PRIORITY);
MAP_IntPrioritySet(FAULT_SYSTICK, SYSTICK_INT_PRIORITY);
//
// Loop forever. All the work is done in interrupt handlers.
//
uint32_t last_time = g_millis;
bool led = false;
while(1)
{
if ((g_millis - last_time) > 500) {
if (led) {
MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, ~GPIO_PIN_0);
led = false;
} else {
MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, GPIO_PIN_0);
led = true;
}
last_time = g_millis;
}
client->loop();
}
return 0;
}
/**
* Creates task to feed data from interrupt to lwIP,
* initializes EMAC0, then initializes lwIP
*/
void init_ethernet(void){/*{{{*/
{ // Enable Ethernet hardware/*{{{*/
uint32_t user0, user1;
/**
* Enable ethernet
* See page 160 of spmu298a
*/
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
//Enable internal PHY
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
// Set Ethernet LED pinouts
// See Page 269 of spmu298a.pdf
MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0);
MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1);
GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0|GPIO_PIN_4);
// Busy wait until MAC ready
while(MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0) == 0);
//Using builtin PHY, so don't need to call GPIOPinTypeEthernetMII()
MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_TYPE_INTERNAL|EMAC_PHY_INT_MDIX_EN|EMAC_PHY_AN_100B_T_FULL_DUPLEX);
// Initialize MAC (see spmu363a.pdf)
// Maybe should optimize burst size
MAP_EMACInit(EMAC0_BASE, g_syshz, EMAC_BCONFIG_MIXED_BURST|EMAC_BCONFIG_PRIORITY_FIXED, 4, 4, 0);
// Set options
// Tune parameters
MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX |
EMAC_CONFIG_CHECKSUM_OFFLOAD |
EMAC_CONFIG_7BYTE_PREAMBLE |
EMAC_CONFIG_IF_GAP_96BITS |
EMAC_CONFIG_USE_MACADDR0 |
EMAC_CONFIG_SA_FROM_DESCRIPTOR |
EMAC_CONFIG_100MBPS|
EMAC_CONFIG_BO_LIMIT_1024),
(EMAC_MODE_RX_STORE_FORWARD |
EMAC_MODE_TX_STORE_FORWARD |
EMAC_MODE_TX_THRESHOLD_64_BYTES |
EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);
//Mac Address saved in user0 and user1 by default
MAP_FlashUserGet(&user0, &user1);
mac_addr[0] = user0 & 0xFF;
mac_addr[1] = user0 >> 8 & 0xFF;
mac_addr[2] = user0 >> 16 & 0xFF;
mac_addr[3] = user1 & 0xFF;
mac_addr[4] = user1 >> 8 & 0xFF;
mac_addr[5] = user1 >> 16 & 0xFF;
MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr );
//Explicitly Disable PTP
EMACTimestampDisable(EMAC0_BASE);
}/*}}}*/
// Lower priority of ISR so *FromISR functions can be safely called
MAP_IntPrioritySet(INT_EMAC0, ETH_ISR_PRIO);
tcpip_init(tcpip_init_cb, NULL);
}/*}}}*/