void SampleInit(void) { /* //UDMAInit(); // Reset SPI //MAP_SPIReset(GSPI_BASE); MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_ON| SPI_CS_ACTIVELOW | SPI_WL_8)); MAP_SPIEnable(GSPI_BASE); MAP_SPICSEnable(GSPI_BASE); MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO); MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO); SPIFIFOLevelSet(GSPI_BASE,1,1); MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX|SPI_INT_DMATX); //MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX); //MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler); osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32); */ UDMAInit(); MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_3, (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_ON| SPI_CS_ACTIVEHIGH | SPI_WL_8)); MAP_SPIEnable(GSPI_BASE); MAP_SPICSEnable(GSPI_BASE); MAP_SPIFIFOEnable(GSPI_BASE,SPI_RX_FIFO); MAP_SPIFIFOEnable(GSPI_BASE,SPI_TX_FIFO); SPIFIFOLevelSet(GSPI_BASE,1,1); MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMARX); //MAP_SPIIntEnable(GSPI_BASE,SPI_INT_DMATX); //MAP_SPIIntRegister(GSPI_BASE,DMAIntHandler); osi_InterruptRegister(INT_GSPI, DMAIntHandler, 32); }
/* * ======== SPICC3200DMA_initHw ======== */ static void SPICC3200DMA_initHw(SPI_Handle handle) { SPICC3200DMA_Object *object = handle->object; SPICC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs; /* Configure the SPI peripheral */ MAP_SPICSDisable(hwAttrs->baseAddr); MAP_SPIDisable(hwAttrs->baseAddr); MAP_SPIReset(hwAttrs->baseAddr); /* * To support 4-32 bit lengths, object->dataSize must be formatted to meet * hardware requirement. */ MAP_SPIConfigSetExpClk(hwAttrs->baseAddr, MAP_PRCMPeripheralClockGet(hwAttrs->spiPRCM), object->bitRate, mode[object->spiMode], frameFormat[object->frameFormat], (hwAttrs->csControl | hwAttrs->pinMode | hwAttrs->turboMode | hwAttrs->csPolarity | ((object->dataSize - 1) << 7))); /* Enable FIFOs, DMA, & interrupts */ MAP_SPIFIFOEnable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); MAP_SPIDmaEnable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); MAP_SPIFIFOLevelSet(hwAttrs->baseAddr, object->txFifoTrigger, object->rxFifoTrigger); }
void SPIInit(){ // Reset SPI MAP_SPIReset(GSPI_BASE); //Enables the transmit and/or receive FIFOs. //Base address is GSPI_BASE, SPI_TX_FIFO || SPI_RX_FIFO are the FIFOs to be enabled MAP_SPIFIFOEnable(GSPI_BASE, SPI_TX_FIFO || SPI_RX_FIFO); // Configure SPI interface MAP_SPIConfigSetExpClk(GSPI_BASE,MAP_PRCMPeripheralClockGet(PRCM_GSPI), SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVELOW | SPI_WL_8)); // Enable SPI for communication MAP_SPIEnable(GSPI_BASE); }
Fd_t spi_Open(char *ifName, unsigned long flags) { unsigned long ulBase; unsigned long ulSpiBitRate; tROMVersion* pRomVersion = (tROMVersion *)(ROM_VERSION_ADDR); //NWP master interface ulBase = LSPI_BASE; //Enable MCSPIA2 MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK); //Disable Chip Select MAP_SPICSDisable(ulBase); //Disable SPI Channel MAP_SPIDisable(ulBase); // Reset SPI MAP_SPIReset(ulBase); // // Configure SPI interface // if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_21 ) { ulSpiBitRate = SPI_RATE_13M; } else if(pRomVersion->ucMinorVerNum == ROM_VER_PG1_32) { ulSpiBitRate = SPI_RATE_13M; } else if(pRomVersion->ucMinorVerNum >= ROM_VER_PG1_33) { ulSpiBitRate = SPI_RATE_20M; } MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI), ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | SPI_CS_ACTIVEHIGH | SPI_WL_32)); if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA)) { g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0; } else { g_ucDMAEnabled = 0; } #ifdef SL_CPU_MODE g_ucDMAEnabled = 0; #endif if(g_ucDMAEnabled) { memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout)); // Set DMA channel cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX); cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX); MAP_SPIFIFOEnable(ulBase,SPI_RX_FIFO); MAP_SPIFIFOEnable(ulBase,SPI_TX_FIFO); MAP_SPIDmaEnable(ulBase,SPI_RX_DMA); MAP_SPIDmaEnable(ulBase,SPI_TX_DMA); MAP_SPIFIFOLevelSet(ulBase,1,1); #if defined(SL_PLATFORM_MULTI_THREADED) osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1); MAP_SPIIntEnable(ulBase,SPI_INT_EOW); osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1); #else MAP_IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler); MAP_IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1); MAP_IntEnable(INT_LSPI); MAP_SPIIntEnable(ulBase,SPI_INT_EOW); g_cDummy = 0x0; #endif } MAP_SPIEnable(ulBase); g_SpiFd = 1; return g_SpiFd; }