void Uart0::isr() {
uint32_t Status;
char data;
Uart0 *object;
// Process UARTA0
if (g_uart0_object != NULL) {
Status = MAP_UARTIntStatus(UARTA0_BASE, true);
MAP_UARTIntClear(UARTA0_BASE, Status);
object = g_uart0_object;
if (Status & UART_INT_RX) {
data = MAP_UARTCharGet(UARTA0_BASE);
if (object->echo)
MAP_UARTCharPut(UARTA0_BASE, data);
object->in_buffer()->push_front_isr(data);
}
if (!object->out_buffer()->is_empty()) {
data = object->out_buffer()->pop_isr();
MAP_UARTCharPut(UARTA0_BASE, data);
}
}
}
STATIC void UARTGenericIntHandler(uint32_t uart_id) {
pyb_uart_obj_t *self;
uint32_t status;
if ((self = pyb_uart_find(uart_id))) {
status = MAP_UARTIntStatus(self->reg, true);
// receive interrupt
if (status & (UART_INT_RX | UART_INT_RT)) {
MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
while (UARTCharsAvail(self->reg)) {
int data = MAP_UARTCharGetNonBlocking(self->reg);
if (MICROPY_STDIO_UART == self->uart_id && data == user_interrupt_char) {
// raise exception when interrupts are finished
mpexception_keyboard_nlr_jump();
}
else if (self->read_buf_len != 0) {
uint16_t next_head = (self->read_buf_head + 1) % self->read_buf_len;
if (next_head != self->read_buf_tail) {
// only store data if room in buf
self->read_buf[self->read_buf_head] = data;
self->read_buf_head = next_head;
}
}
}
}
}
}
//--------------------------------
extern "C" void esp8266_UARTIntHandler(void) {
uint32_t ui32Ints = MAP_UARTIntStatus(UART_BASE, true);
MAP_UARTIntClear(UART_BASE, ui32Ints);
if (pTheOneAndOnlyEsp8266) {
pTheOneAndOnlyEsp8266->OnUart(ui32Ints);
}
}
static void cc32xx_int_handler(struct mgos_uart_state *us) {
if (us == NULL) return;
struct cc32xx_uart_state *ds = (struct cc32xx_uart_state *) us->dev_data;
uint32_t int_st = MAP_UARTIntStatus(ds->base, true /* masked */);
us->stats.ints++;
uint32_t int_dis = UART_TX_INTS;
if (int_st & UART_INT_OE) {
us->stats.rx_overflows++;
HWREG(ds->base + UART_O_ECR) = 0xff;
}
if (int_st & (UART_RX_INTS | UART_TX_INTS)) {
if (int_st & UART_RX_INTS) {
us->stats.rx_ints++;
struct cs_rbuf *irxb = &ds->isr_rx_buf;
cc32xx_uart_rx_bytes(ds->base, irxb);
if (us->cfg.rx_fc_type == MGOS_UART_FC_SW &&
irxb->used >= CC32xx_UART_ISR_RX_BUF_FC_THRESH && !us->xoff_sent) {
MAP_UARTCharPut(ds->base, MGOS_UART_XOFF_CHAR);
us->xoff_sent = true;
}
/* Do not disable RX ints if we have space in the ISR buffer. */
if (irxb->avail == 0) int_dis |= UART_RX_INTS;
}
if (int_st & UART_TX_INTS) us->stats.tx_ints++;
mgos_uart_schedule_dispatcher(us->uart_no, true /* from_isr */);
}
MAP_UARTIntDisable(ds->base, int_dis);
MAP_UARTIntClear(ds->base, int_st);
}
static int int_uart_rx_get_flag( elua_int_resnum resnum, int clear )
{
int flag = ( MAP_UARTIntStatus( uart_base[ resnum ], false ) & uart_int_mask ) == uart_int_mask ? 1 : 0;
if( clear )
MAP_UARTIntClear( uart_base[ resnum ], uart_int_mask );
return flag;
}
void rt_hw_uart_isr(struct rt_lm3s_serial* serial)
{
rt_device_t device;
rt_uint32_t status;
device = (struct rt_device*)serial;
status = MAP_UARTIntStatus(serial->hw_base, true);
/* clear interrupt status */
MAP_UARTIntClear(serial->hw_base, status);
if (device->flag & RT_DEVICE_FLAG_INT_RX)
{
char ch;
rt_base_t level;
while (MAP_UARTCharsAvail(serial->hw_base))
{
ch = MAP_UARTCharGetNonBlocking(serial->hw_base);
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* read character */
serial->rx_buffer[serial->save_index] = ch;
serial->save_index ++;
if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
serial->save_index = 0;
/* if the next position is read index, discard this 'read char' */
if (serial->save_index == serial->read_index)
{
serial->read_index ++;
if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
serial->read_index = 0;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if(device->rx_indicate != RT_NULL)
{
rt_int32_t length;
length = serial->save_index - serial->read_index;
if (length < 0) length += RT_UART_RX_BUFFER_SIZE;
device->rx_indicate(device, length);
}
}
}
void UARTIntHandler()
{
u32 temp;
int c;
temp = MAP_UARTIntStatus(uart_base[ CON_UART_ID ], true);
MAP_UARTIntClear(uart_base[ CON_UART_ID ], temp);
while( MAP_UARTCharsAvail( uart_base[ CON_UART_ID ] ) )
{
c = MAP_UARTCharGetNonBlocking( uart_base[ CON_UART_ID ] );
buf_write( BUF_ID_UART, CON_UART_ID, ( t_buf_data* )&c );
}
}
void Uart4IntHandler(void)
{
UartChannelData* const pChannelData = uart2UartChannelData[UART_4];
const uint32_t status = MAP_UARTIntStatus(pChannelData->base, true);
MAP_UARTIntClear(pChannelData->base, status);
if (status & (UART_INT_RX | UART_INT_RT))
{
uartReadIntHandler(pChannelData);
}
if (status & UART_INT_TX)
{
uartWriteIntHandler(pChannelData);
}
}
void receiveMessage(){
int i;
unsigned long ulStatus;
//Get status of UART interrupt
ulStatus = MAP_UARTIntStatus(UARTA1_BASE, true);
UARTIntClear(UARTA1_BASE, ulStatus );
//Create a small delay to ensure that the hardware functions correctly
MAP_UtilsDelay(80000);
for(i = 0; i < 8; i++){
//Get the character from UART1 register
MessageRx[i] = MAP_UARTCharGet(UARTA1_BASE);
MAP_UtilsDelay(80000);
//Draw the received char on the OLED
drawChar(6*i, 64, MessageRx[i], WHITE, BLACK, 0x01);
MAP_UtilsDelay(80000);
}
UARTIntEnable(UARTA1_BASE, UART_INT_RX|UART_INT_RT);
}
//*****************************************************************************
//
// The interrupt handler for UART1. This interrupt will occur when a DMA
// transfer is complete using the UART1 uDMA channel. It will also be
// triggered if the peripheral signals an error. This interrupt handler
// will set a flag when each scatter-gather transfer is complete (one for each
// of UART RX and TX).
//
//*****************************************************************************
void
UART1IntHandler(void)
{
unsigned long ulStatus;
//
// Read the interrupt status of the UART.
//
ulStatus = MAP_UARTIntStatus(UART1_BASE, 1);
//
// Clear any pending status, even though there should be none since no UART
// interrupts were enabled. If UART error interrupts were enabled, then
// those interrupts could occur here and should be handled. Since uDMA is
// used for both the RX and TX, then neither of those interrupts should be
// enabled.
//
MAP_UARTIntClear(UART1_BASE, ulStatus);
//
// Count the number of times this interrupt occurred.
//
g_ulDMAIntCount++;
//
// Check the UART TX DMA channel to see if it is enabled. When it is
// finished with the transfer it will be automatically disabled.
//
if(!MAP_uDMAChannelIsEnabled(UDMA_CHANNEL_UART1TX))
{
g_bTXdone= 1;
}
//
// Check the UART RX DMA channel to see if it is enabled. When it is
// finished with the transfer it will be automatically disabled.
//
if(!MAP_uDMAChannelIsEnabled(UDMA_CHANNEL_UART1RX))
{
g_bRXdone= 1;
}
}
void HardwareSerial::UARTIntHandler(void)
{
unsigned long ulInts;
long lChar;
/* Get and clear the current interrupt source(s) */
ulInts = MAP_UARTIntStatus(UART_BASE, true);
MAP_UARTIntClear(UART_BASE, ulInts);
/* Are we being interrupted because the TX FIFO has space available? */
if(ulInts & UART_INT_TX) {
/* Move as many bytes as we can into the transmit FIFO. */
primeTransmit(UART_BASE);
/* If the output buffer is empty, turn off the transmit interrupt. */
if(TX_BUFFER_EMPTY) {
MAP_UARTIntDisable(UART_BASE, UART_INT_TX);
}
}
if(ulInts & (UART_INT_RT | UART_INT_TX)) {
while(MAP_UARTCharsAvail(UART_BASE)) {
/* Read a character */
lChar = MAP_UARTCharGetNonBlocking(UART_BASE);
/* If there is space in the receive buffer, put the character
* there, otherwise throw it away. */
uint8_t volatile full = RX_BUFFER_FULL;
if(full) break;
rxBuffer[rxWriteIndex] = (unsigned char)(lChar & 0xFF);
rxWriteIndex = ((rxWriteIndex) + 1) % rxBufferSize;
/* If we wrote anything to the transmit buffer, make sure it actually
* gets transmitted. */
}
primeTransmit(UART_BASE);
MAP_UARTIntEnable(UART_BASE, UART_INT_TX);
}
}
static int int_uart_rx_get_status( elua_int_resnum resnum )
{
return ( MAP_UARTIntStatus( uart_base[ resnum ], false ) & uart_int_mask ) == uart_int_mask ? 1 : 0;
}
//*****************************************************************************
//!
//! The interrupt handler for UART0. This interrupt will occur when a DMA
//! transfer is complete using the UART0 uDMA channel.This interrupt handler will
//! switch between receive ping-pong buffers A and B. It will also restart a TX
//! uDMA transfer if the prior transfer is complete. This will keep the UART
//! running continuously (looping TX data back to RX).
//!
//! \param None
//!
//! \return None
//*****************************************************************************
void
UART0IntHandler(void)
{
unsigned long ulStatus;
unsigned long ulMode;
//
// Read the interrupt status of the UART.
//
ulStatus = MAP_UARTIntStatus(UARTA0_BASE, 1);
//
// Clear any pending status, even though there should be none since no UART
// interrupts were enabled.
//
MAP_UARTIntClear(UARTA0_BASE, ulStatus);
if(uiCount<6)
{
//
// Check the DMA control table to see if the ping-pong "A" transfer is
// complete. The "A" transfer uses receive buffer "A", and the primary
// control structure.
//
ulMode = MAP_uDMAChannelModeGet(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT);
//
// If the primary control structure indicates stop, that means the "A"
// receive buffer is done. The uDMA controller should still be receiving
// data into the "B" buffer.
//
if(ulMode == UDMA_MODE_STOP)
{
//
// Increment a counter to indicate data was received into buffer A.
//
g_ulRxBufACount++;
//
// Set up the next transfer for the "A" buffer, using the primary
// control structure. When the ongoing receive into the "B" buffer is
// done, the uDMA controller will switch back to this one.
//
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufA),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufA, UDMA_DST_INC_8);
}
//
// Check the DMA control table to see if the ping-pong "B" transfer is
// complete. The "B" transfer uses receive buffer "B", and the alternate
// control structure.
//
ulMode = MAP_uDMAChannelModeGet(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT);
//
// If the alternate control structure indicates stop, that means the "B"
// receive buffer is done. The uDMA controller should still be receiving
// data into the "A" buffer.
//
if(ulMode == UDMA_MODE_STOP)
{
//
// Increment a counter to indicate data was received into buffer A.
//
g_ulRxBufBCount++;
//
// Set up the next transfer for the "B" buffer, using the alternate
// control structure. When the ongoing receive into the "A" buffer is
// done, the uDMA controller will switch back to this one.
//
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT,
UDMA_MODE_PINGPONG, sizeof(g_ucRxBufB),UDMA_SIZE_8,
UDMA_ARB_4,(void *)(UARTA0_BASE + UART_O_DR),
UDMA_SRC_INC_NONE, g_ucRxBufB, UDMA_DST_INC_8);
}
//
// If the UART0 DMA TX channel is disabled, that means the TX DMA transfer
// is done.
//
if(!MAP_uDMAChannelIsEnabled(UDMA_CH9_UARTA0_TX))
{
g_ulTxCount++;
//
// Start another DMA transfer to UART0 TX.
//
UDMASetupTransfer(UDMA_CH9_UARTA0_TX| UDMA_PRI_SELECT, UDMA_MODE_BASIC,
sizeof(g_ucTxBuf),UDMA_SIZE_8, UDMA_ARB_4,g_ucTxBuf, UDMA_SRC_INC_8,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_DST_INC_NONE);
//
// The uDMA TX channel must be re-enabled.
//
MAP_uDMAChannelEnable(UDMA_CH9_UARTA0_TX);
}
}
else
{
UARTDone=1;
MAP_UARTIntUnregister(UARTA0_BASE);
}
}
uint32_t cc32xx_uart_raw_ints(int uart_no) {
uint32_t base = cc32xx_uart_get_base(uart_no);
return MAP_UARTIntStatus(base, false /* masked */);
}
//------------------------------------------------------------------------------
//new
void uart0_int_handler()
{
unsigned long const ist = MAP_UARTIntStatus(UART_BASE, TRUE);
if (ist & (UART_INT_RX | UART_INT_RT))
{
MAP_UARTIntClear(UART_BASE, UART_INT_RX|UART_INT_RT);
long b;
while(MAP_UARTCharsAvail(UART_BASE))
{
b = MAP_UARTCharGetNonBlocking(UART_BASE);
if (b == -1 || (char)b == '$' || g_rx_buf_len >= UART_BUF_SZ)
{
g_rx_buf_len = 0;
g_rx_buf[g_rx_buf_len++] = b;
}else
{
if (b == 0x0D && g_rx_buf[0] == '$' && g_rx_buf[g_rx_buf_len-3] == '*') // +ёыш ъюэхЎ яръхЄр
{
if ( g_rx_buf_len > 10)
{
unsigned char crc;
if (g_rx_buf[--g_rx_buf_len] > '9')
crc = 0x0A + g_rx_buf[g_rx_buf_len]-'A';
else
crc = (g_rx_buf[g_rx_buf_len]-'0');
if (g_rx_buf[--g_rx_buf_len] > '9')
crc |= (0x0A + g_rx_buf[g_rx_buf_len]-'A')<< 4;
else
crc |= (g_rx_buf[g_rx_buf_len]-'0')<< 4;
g_rx_buf_len-=2;
do{
crc ^= g_rx_buf[g_rx_buf_len];
}while( --g_rx_buf_len );
if (!crc) // CRC
{
health_count = 0;
gps_info.pack_found++;
/* Parse packet */
if( !strncmp((char*)g_rx_buf, "$GPGGA", 6) )
{
ProcessGPGGA(&g_rx_buf[7]);
st[1] =hw_time();
}
else if( !strncmp((char*)g_rx_buf, "$GPRMC", 6))
{
ProcessGPRMC(&g_rx_buf[7]);
//
gps_pps_counter=0;
//
//
st[0] =hw_time();
}
}else
{
gps_info.crc_error++;
}
}
g_rx_buf_len = 0;
}else
if (b != 0x0A)
g_rx_buf[g_rx_buf_len++] = b;
}
}//while
}
/////
if (ist & UART_INT_TX)
{
MAP_UARTIntClear(UART_BASE, UART_INT_TX);
tx_pkt_snd_one();
}
}
