예제 #1
0
void Clock_init(void)
{
// Init system clock
  /* System clock initialization */
  /* SIM_SCGC5: PORTA=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
  /* SIM_SOPT2: PLLFLLSEL=0 */
  SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
  /* SIM_SOPT2: TPMSRC=1 */
  SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
			   SIM_SOPT2_TPMSRC(0x02)
			  )) | (uint32_t)(
			   SIM_SOPT2_TPMSRC(0x01)
			  ));                      /* Set the TPM clock */
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* PORTA_PCR19: ISF=0,MUX=0 */
  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* MCG_SC: FCRDIV=1 */
  MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)(
			MCG_SC_FCRDIV(0x06)
		   )) | (uint8_t)(
			MCG_SC_FCRDIV(0x01)
		   ));
  /* Switch to FEE Mode */
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=1 */
  MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK | MCG_C2_IRCS_MASK);
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC0_CR = OSC_CR_ERCLKEN_MASK;
  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
  /* MCG_C4: DMX32=0,DRST_DRS=1 */
  MCG_C4 = (uint8_t)((MCG_C4 & (uint8_t)~(uint8_t)(
			MCG_C4_DMX32_MASK |
			MCG_C4_DRST_DRS(0x02)
		   )) | (uint8_t)(
			MCG_C4_DRST_DRS(0x01)
		   ));
  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
  MCG_C5 = MCG_C5_PRDIV0(0x00);
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
  MCG_C6 = MCG_C6_VDIV0(0x00);
  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG_S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
  }
  /*** End of PE initialization code after reset ***/

}
/*************************************************************************
* 函数名称:WORD32 Timer_Init()
* 功能说明:初始化计时器
* 输入参数:无
* 输出参数:无
* 返 回 值:SW_ERROR: 操作失败
*           SW_OK 操作成功
* 其它说明:无
**************************************************************************/
WORD32 Timer_Init()
{
    WORD32 dwData = 0; // For temp value of register

    MCG_SC &= (~MCG_SC_FCRDIV_MASK);     // Do this before set value of FCRDIV to evoid wrong masking
    MCG_SC |= MCG_SC_FCRDIV(2);          // We choose to divided clock by 4
    MCG_C2 |= MCG_C2_IRCS_MASK;          // And we choose the fast internal refenced clock(4MHz),
                                         // So final clock is 1Mhz.
    MCG_C1 |= MCG_C1_IRCLKEN_MASK;       // Then turn on MCGIRCLK and it works even in stop mode
    SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   // Enable LPTMR software accessing

    LPTMR0_CSR &= ~LPTMR_CSR_TEN_MASK;   // Turn off LPTMR before LPTMR register configration
    dwData |= (LPTMR_CSR_TIE_MASK\
              |LPTMR_CSR_TCF_MASK);      // We do this to reduce operations of register to save time
    LPTMR0_CSR = dwData;                 // In this case, we just operate register for once.
    LPTMR0_PSR |= LPTMR_PSR_PBYP_MASK;   // We do not need to divided the clock any more here
    LPTMR0_PSR &= (~LPTMR_PSR_PCS_MASK); // Choose MCGIRCLK as the clock source (1MHz)
    LPTMR0_CMR = (1025);                 // Then turn it as a period in 1ms

    LPTMR0_CSR |= LPTMR_CSR_TEN_MASK;    // After all, we turn on LPTMR and start counting
    
    NVIC_ICPR |= 1 << 28;
    NVIC_ISER |= 1 << 28;                // Enable interrupt
    return SW_OK;                        // That is all
}
예제 #3
0
status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig)
{
    assert(targetConfig);

    /*
     * If switch between LIRC8M and LIRC2M, need to switch to HIRC mode first,
     * because could not switch directly.
     */
    if ((kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL) && (kMCGLITE_ClkSrcLirc == targetConfig->outSrc) &&
        (MCG_C2_IRCS_VAL != targetConfig->ircs))
    {
        MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCGLITE_ClkSrcHirc);
        while (kMCGLITE_ClkSrcHirc != MCG_S_CLKST_VAL)
        {
        }
    }

    /* Set configuration now. */
    MCG->SC = MCG_SC_FCRDIV(targetConfig->fcrdiv);
    MCG->MC = MCG_MC_HIRCEN(targetConfig->hircEnableInNotHircMode) | MCG_MC_LIRC_DIV2(targetConfig->lircDiv2);
    MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | MCG_C2_IRCS(targetConfig->ircs);
    MCG->C1 = MCG_C1_CLKS(targetConfig->outSrc) | targetConfig->irclkEnableMode;

    /*
     * If external oscillator used and MCG_Lite is set to EXT mode, need to
     * wait for the OSC stable.
     */
    if ((MCG->C2 & MCG_C2_EREFS0_MASK) && (kMCGLITE_ClkSrcExt == targetConfig->outSrc))
    {
        while (!(MCG->S & MCG_S_OSCINIT0_MASK))
        {
        }
    }

    /* Wait for clock source change completed. */
    while (targetConfig->outSrc != MCG_S_CLKST_VAL)
    {
    }

    return kStatus_Success;
}
예제 #4
0
status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
{
    uint32_t mcgOutClkState = MCG_S_CLKST_VAL;
    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL;
    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;

#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
    /* If MCGIRCLK is used as system clock source. */
    if (kMCG_ClkOutStatInt == mcgOutClkState)
    {
        /* If need to change MCGIRCLK source or driver, return error. */
        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
        {
            return kStatus_MCG_SourceUsed;
        }
    }
#endif

    /* If need to update the FCRDIV. */
    if (fcrdiv != curFcrdiv)
    {
        /* If fast IRC is in use currently, change to slow IRC. */
        if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
        {
            MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
            while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
            {
            }
        }
        /* Update FCRDIV. */
        MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv);
    }

    /* Set internal reference clock selection. */
    MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs));
    MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode;

    /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
    if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable))
    {
        while (MCG_S_IRCST_VAL != ircs)
        {
        }
    }

    return kStatus_Success;
}
예제 #5
0
파일: bsp_cm.c 프로젝트: Vinhuit/Freescale
/* ===================================================================*/
LDD_TError Cpu_SetClockConfiguration(LDD_TClockConfiguration ModeID)
{
  if (ModeID > 0x02U) {
    return ERR_RANGE;                  /* Undefined clock configuration requested requested */
  }
  switch (ModeID) {
    case CPU_CLOCK_CONFIG_0:
      if (ClockConfigurationID == 2U) {
        /* Clock configuration 0 and clock configuration 2 use different clock configuration */
        /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                      SIM_CLKDIV1_OUTDIV2(0x01) |
                      SIM_CLKDIV1_OUTDIV3(0x04) |
                      SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */
        Cpu_SetMCG(0U);                /* Update clock source setting */
      }
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                    SIM_CLKDIV1_OUTDIV2(0x01) |
                    SIM_CLKDIV1_OUTDIV3(0x02) |
                    SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
      /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
      SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */
      /* SIM_SOPT2: PLLFLLSEL=1 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
      /* SIM_SOPT1: OSC32KSEL=0 */
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
      break;
    case CPU_CLOCK_CONFIG_1:
      if (ClockConfigurationID == 2U) {
        /* Clock configuration 1 and clock configuration 2 use different clock configuration */
        /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
        SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                      SIM_CLKDIV1_OUTDIV2(0x01) |
                      SIM_CLKDIV1_OUTDIV3(0x04) |
                      SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */
        Cpu_SetMCG(0U);                /* Update clock source setting */
      }
      /* SIM_CLKDIV1: OUTDIV1=9,OUTDIV2=9,OUTDIV3=9,OUTDIV4=9,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x09) |
                    SIM_CLKDIV1_OUTDIV2(0x09) |
                    SIM_CLKDIV1_OUTDIV3(0x09) |
                    SIM_CLKDIV1_OUTDIV4(0x09); /* Update system prescalers */
      /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
      SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */
      /* SIM_SOPT2: PLLFLLSEL=1 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
      /* SIM_SOPT1: OSC32KSEL=0 */
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
      break;
    case CPU_CLOCK_CONFIG_2:
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                    SIM_CLKDIV1_OUTDIV2(0x01) |
                    SIM_CLKDIV1_OUTDIV3(0x04) |
                    SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */
      if ((MCG_C2 & MCG_C2_IRCS_MASK) == 0x00U) {
        /* MCG_SC: FCRDIV=1 */
        MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)(
                  MCG_SC_FCRDIV(0x06)
                 )) | (uint8_t)(
                  MCG_SC_FCRDIV(0x01)
                 ));
      } else {
        /* MCG_C2: IRCS=0 */
        MCG_C2 &= (uint8_t)~(uint8_t)(MCG_C2_IRCS_MASK);
        while((MCG_S & MCG_S_IRCST_MASK) != 0x00U) { /* Check that the source internal reference clock is slow clock. */
        }
        /* MCG_SC: FCRDIV=1 */
        MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)(
                  MCG_SC_FCRDIV(0x06)
                 )) | (uint8_t)(
                  MCG_SC_FCRDIV(0x01)
                 ));
        /* MCG_C2: IRCS=1 */
        MCG_C2 |= MCG_C2_IRCS_MASK;
        while((MCG_S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the source internal reference clock is fast clock. */
        }
      }
      Cpu_SetMCG(1U);                  /* Update clock source setting */
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                    SIM_CLKDIV1_OUTDIV2(0x00) |
                    SIM_CLKDIV1_OUTDIV3(0x00) |
                    SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
      /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
      SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */
      /* SIM_SOPT2: PLLFLLSEL=1 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
      /* SIM_SOPT1: OSC32KSEL=0 */
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
      break;
    default:
      break;
  }
  LDD_SetClockConfiguration(ModeID);   /* Call all LDD components to update the clock configuration */
  ClockConfigurationID = ModeID;       /* Store clock configuration identifier */
  return ERR_OK;
}
예제 #6
0
파일: bsp_cm.c 프로젝트: BillyZhangZ/wifi
/*
** ===================================================================
**     Method      :  Cpu_SetClockConfiguration (component MK22FN512VDC12)
**
**     Description :
**         Calling of this method will cause the clock configuration
**         change and reconfiguration of all components according to
**         the requested clock configuration setting.
**     Parameters  :
**         NAME            - DESCRIPTION
**         ModeID          - Clock configuration identifier
**     Returns     :
**         ---             - ERR_OK - OK.
**                           ERR_RANGE - Mode parameter out of range
** ===================================================================
*/
LDD_TError Cpu_SetClockConfiguration(LDD_TClockConfiguration ModeID)
{
  if (ModeID > 0x03U) {
    return ERR_RANGE;                  /* Undefined clock configuration requested requested */
  }

  if (0x03U == ClockConfigurationID) {
    if ((CPU_CLOCK_CONFIG_1 == ModeID) || ( CPU_CLOCK_CONFIG_2 == ModeID))
        return ERR_FAILED;
    Cpu_SetMCGClockInModePEE(ModeID);
  }

  if (0x03U == ModeID) {
    if ((CPU_CLOCK_CONFIG_1 == ClockConfigurationID) || ( CPU_CLOCK_CONFIG_2 == ClockConfigurationID))
        return ERR_FAILED;
    Cpu_SetMCGClockInModePEE(ModeID); 
  }

  switch (ModeID) {
    case CPU_CLOCK_CONFIG_0:
      if (ClockConfigurationID == 2U) {
        /* Clock configuration 0 and clock configuration 2 use different clock configuration */
	/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,*/
	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
	              SIM_CLKDIV1_OUTDIV2(0x01) |
		      SIM_CLKDIV1_OUTDIV3(0x04) |
		      SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */
        Cpu_SetMCG(0U);                /* Update clock source setting */
      }
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                    SIM_CLKDIV1_OUTDIV2(0x01) |
                    SIM_CLKDIV1_OUTDIV3(0x03) |
                    SIM_CLKDIV1_OUTDIV4(0x02); /* Update system prescalers */
#if (BSPCFG_USB_CLK_FROM_IRC48M)
        SIM_CLKDIV2  =  0;
        SIM_SOPT2   |=  SIM_SOPT2_PLLFLLSEL(0x03);
        SIM_SCGC4   |= (SIM_SCGC4_USBOTG_MASK);
        /* Enable IRC 48MHz for USB module */
        USB_CLK_RECOVER_IRC_EN = 0x03;
#else
      /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
      SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* Update USB clock prescalers */
      /* SIM_SOPT2: PLLFLLSEL=0x01 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */
      /* SIM_SOPT1: OSC32KSEL=0 */
#endif
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
      break;
    case CPU_CLOCK_CONFIG_1:
      if (ClockConfigurationID == 2U) {
        /* Clock configuration 1 and clock configuration 2 use different clock configuration */
        /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
	              SIM_CLKDIV1_OUTDIV2(0x01) |
		      SIM_CLKDIV1_OUTDIV3(0x04) |
		      SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */
        Cpu_SetMCG(0U);                /* Update clock source setting */
      }
      /* SIM_CLKDIV1: OUTDIV1=9,OUTDIV2=9,OUTDIV3=9,OUTDIV4=9,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x09) |
                    SIM_CLKDIV1_OUTDIV2(0x09) |
                    SIM_CLKDIV1_OUTDIV3(0x09) |
                    SIM_CLKDIV1_OUTDIV4(0x09); /* Update system prescalers */
      /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
        SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK;
      /* SIM_SOPT2: PLLFLLSEL=0x01 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01);
      /* SIM_SOPT1: OSC32KSEL=0 */
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
      break;
    case CPU_CLOCK_CONFIG_2:
     /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??*/
     SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                   SIM_CLKDIV1_OUTDIV2(0x01) |
	           SIM_CLKDIV1_OUTDIV3(0x04) |
	           SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */
     if ((MCG_C2 & MCG_C2_IRCS_MASK) == 0x00U) {
       /* MCG_SC: FCRDIV=1 */
         MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)(
	           MCG_SC_FCRDIV(0x06)
		  )) | (uint8_t)(
		   MCG_SC_FCRDIV(0x01)
		  ));
      } else {
        /* MCG_C2: IRCS=0 */
        MCG_C2 &= (uint8_t)~(uint8_t)(MCG_C2_IRCS_MASK);
	while((MCG_S & MCG_S_IRCST_MASK) != 0x00U) { /* Check that the source internal reference clock is slow clock. */
	}
        /* MCG_SC: FCRDIV=1 */
        MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)(
                  MCG_SC_FCRDIV(0x06)
		 )) | (uint8_t)(
		  MCG_SC_FCRDIV(0x01)
		 ));
	/* MCG_C2: IRCS=1 */
        MCG_C2 |= MCG_C2_IRCS_MASK;
	while((MCG_S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the source internal reference clock is fast clock. */
	}
      }
      Cpu_SetMCG(1U);                  /* Update clock source setting */
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                    SIM_CLKDIV1_OUTDIV2(0x00) |
                    SIM_CLKDIV1_OUTDIV3(0x00) |
                    SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
      /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
        SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK;
      /* SIM_SOPT2: PLLFLLSEL=1 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */
	  /* SIM_SOPT1: OSC32KSEL=0 */
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
      break;
	case CPU_CLOCK_CONFIG_3:
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
      SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                    SIM_CLKDIV1_OUTDIV2(0x01) |
                    SIM_CLKDIV1_OUTDIV3(0x04) |
                    SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */

#if (BSPCFG_USB_CLK_FROM_IRC48M)
        SIM_CLKDIV2  =  0;
        SIM_SOPT2   |=  SIM_SOPT2_PLLFLLSEL(0x03);
        SIM_SCGC4   |= (SIM_SCGC4_USBOTG_MASK);
        /* Enable IRC 48MHz for USB module */
        USB_CLK_RECOVER_IRC_EN = 0x03;
#else
      /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
      SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK;
      /* SIM_SOPT2: PLLFLLSEL=1 */
      SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */
#endif


	   /* SIM_SOPT1: OSC32KSEL=0 */
      SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
	  break;
    default:
      break;
  }
  LDD_SetClockConfiguration(ModeID);   /* Call all LDD components to update the clock configuration */
  ClockConfigurationID = ModeID;       /* Store clock configuration identifier */
  return ERR_OK;
}
static void SetMCGRegisters()
{
  /*
  *  MCGIRCKLK - DISABLED
  *  MCGOUTCLK - 4MHz
  *  MCGFLLCLK - DISABLED
  *  MCGFFCLK - DISABLED
  *  *****FROM SIM SETTINGS*****
  */
  MCG->C1 = MCG_C1_CLKS(1)|MCG_C1_FRDIV(0)|((1<<MCG_C1_IREFS_SHIFT)&MCG_C1_IREFS_MASK)|((0<<MCG_C1_IRCLKEN_SHIFT)&MCG_C1_IRCLKEN_MASK)|((0<<MCG_C1_IREFSTEN_SHIFT)&MCG_C1_IREFSTEN_MASK);

  MCG->C2 = ((0<<MCG_C2_LOCRE0_SHIFT)&MCG_C2_LOCRE0_MASK)|((0<<MCG_C2_FCFTRIM_SHIFT)&MCG_C2_FCFTRIM_MASK)|MCG_C2_RANGE0(0)|((0<<MCG_C2_HGO0_SHIFT)&MCG_C2_HGO0_MASK)|((1<<MCG_C2_EREFS0_SHIFT)&MCG_C2_EREFS0_MASK)|((1<<MCG_C2_LP_SHIFT)&MCG_C2_LP_MASK)|((1<<MCG_C2_IRCS_SHIFT)&MCG_C2_IRCS_MASK);

  MCG->C4 |= ((1<<MCG_C4_DMX32_SHIFT)&MCG_C4_DMX32_MASK)|MCG_C4_DRST_DRS(0);//OR'D TO PRESERVE FACTORY TRIM SETTINGS
  //MCG_C6 RESETS TO THE DESIRED VALUE(CME CLEARED)

  MCG->SC = ((0<<MCG_SC_ATME_SHIFT)&MCG_SC_ATME_MASK)|((1<<MCG_SC_ATMS_SHIFT)&MCG_SC_ATMS_MASK)|((0<<MCG_SC_FLTPRSRV_SHIFT)&MCG_SC_FLTPRSRV_MASK)|MCG_SC_FCRDIV(0);


  return;
}
예제 #8
0
파일: Cpu.c 프로젝트: zhangsaisai/SEMG
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{

  /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/

  /*** ### MKL25Z128VLK4 "Cpu" init code ... ***/
  /*** PE initialization code after reset ***/
  SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
  /* Disable the WDOG module */
  /* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */
  SIM_COPC = SIM_COPC_COPT(0x00);                                   

  /* System clock initialization */
  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */
  /* SIM_SCGC5: PORTC=1,PORTA=1 */
  SIM_SCGC5 |= (SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
  if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
    /* PMC_REGSC: ACKISO=1 */
    PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
  }
  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
  /* SIM_SOPT2: PLLFLLSEL=1 */
  SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
  /* SIM_SOPT2: TPMSRC=1 */
  SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
               SIM_SOPT2_TPMSRC(0x02)
              )) | (uint32_t)(
               SIM_SOPT2_TPMSRC(0x01)
              ));                      /* Set the TPM clock */
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));                                   
  /* PORTA_PCR19: ISF=0,MUX=0 */
  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));                                   
  /* MCG_SC: FCRDIV=1 */
  MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)(
            MCG_SC_FCRDIV(0x06)
           )) | (uint8_t)(
            MCG_SC_FCRDIV(0x01)
           ));                                  
  /* Switch to FBE Mode */
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=1 */
  MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK | MCG_C2_IRCS_MASK);                                   
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC0_CR = OSC_CR_ERCLKEN_MASK;                                   
  /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);                                   
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));                                   
  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
  MCG_C5 = MCG_C5_PRDIV0(0x03);                                   
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
  MCG_C6 = MCG_C6_VDIV0(0x00);                                   
  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  /* Switch to PBE Mode */
  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
  MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));                                   
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
  }
  /* Switch to PEE Mode */
  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);                                   
  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
  }
  /*** End of PE initialization code after reset ***/

  /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/

}