static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); return MCDisassembler_Success; }
static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); unsigned Reg = fieldFromInstruction(Insn, 6, 5); unsigned Base = fieldFromInstruction(Insn, 11, 5); Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); // MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); // The immediate field of an LD/ST instruction is scaled which means it must // be multiplied (when decoding) by the size (in bytes) of the instructions' // data format. // .b - 1 byte // .h - 2 bytes // .w - 4 bytes // .d - 8 bytes switch(MCInst_getOpcode(Inst)) { default: //assert (0 && "Unexpected instruction"); return MCDisassembler_Fail; break; case Mips_LD_B: case Mips_ST_B: MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); break; case Mips_LD_H: case Mips_ST_H: MCInst_addOperand(Inst, MCOperand_CreateImm(Offset << 1)); break; case Mips_LD_W: case Mips_ST_W: MCInst_addOperand(Inst, MCOperand_CreateImm(Offset << 2)); break; case Mips_LD_D: case Mips_ST_D: MCInst_addOperand(Inst, MCOperand_CreateImm(Offset << 3)); break; } return MCDisassembler_Success; }
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { // Currently only hardware register 29 is supported. if (RegNo != 29) return MCDisassembler_Fail; MCInst_addOperand(Inst, MCOperand_CreateReg(Mips_HWR29)); return MCDisassembler_Success; }
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { if (RegNo > 31) return MCDisassembler_Fail; unsigned Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); return MCDisassembler_Success; }
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 3) return MCDisassembler_Fail; MCInst_addOperand(Inst, MCOperand_CreateReg(FCCRegDecoderTable[RegNo])); return MCDisassembler_Success; }
/// translateRegister - Translates an internal register to the appropriate LLVM /// register, and appends it as an operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param reg - The Reg to append. static void translateRegister(MCInst *mcInst, Reg reg) { //#define ENTRY(x) X86_x, #define ENTRY(x) X86_##x, uint8_t llvmRegnums[] = { ALL_REGS 0 }; #undef ENTRY uint8_t llvmRegnum = llvmRegnums[reg]; MCInst_addOperand(mcInst, MCOperand_CreateReg(llvmRegnum)); }
/// translateSrcIndex - Appends a source index operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param insn - The internal instruction. static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn) { unsigned baseRegNo; MCOperand *segmentReg; MCOperand *baseReg; if (insn->mode == MODE_64BIT) baseRegNo = insn->prefixPresent[0x67] ? X86_ESI : X86_RSI; else if (insn->mode == MODE_32BIT) baseRegNo = insn->prefixPresent[0x67] ? X86_SI : X86_ESI; else { // assert(insn->mode == MODE_16BIT); baseRegNo = insn->prefixPresent[0x67] ? X86_ESI : X86_SI; } baseReg = MCOperand_CreateReg(baseRegNo); MCInst_addOperand(mcInst, baseReg); segmentReg = MCOperand_CreateReg(segmentRegnums[insn->segmentOverride]); MCInst_addOperand(mcInst, segmentReg); return false; }
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = QFPRegDecoderTable[RegNo]; if (Reg == ~0U) return MCDisassembler_Fail; MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); return MCDisassembler_Success; }
/// translateDstIndex - Appends a destination index operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param insn - The internal instruction. static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn) { unsigned baseRegNo; MCOperand *baseReg; if (insn->mode == MODE_64BIT) baseRegNo = insn->prefixPresent[0x67] ? X86_EDI : X86_RDI; else if (insn->mode == MODE_32BIT) baseRegNo = insn->prefixPresent[0x67] ? X86_DI : X86_EDI; else { // assert(insn->mode == MODE_16BIT); baseRegNo = insn->prefixPresent[0x67] ? X86_EDI : X86_DI; } baseReg = MCOperand_CreateReg(baseRegNo); MCInst_addOperand(mcInst, baseReg); return false; }
/// translateRMMemory - Translates a memory operand stored in the Mod and R/M /// fields of an internal instruction (and possibly its SIB byte) to a memory /// operand in LLVM's format, and appends it to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param insn - The instruction to extract Mod, R/M, and SIB fields /// from. /// @return - 0 on success; nonzero otherwise static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn) { // Addresses in an MCInst are represented as five operands: // 1. basereg (register) The R/M base, or (if there is a SIB) the // SIB base // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified // scale amount // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) // the index (which is multiplied by the // scale amount) // 4. displacement (immediate) 0, or the displacement if there is one // 5. segmentreg (register) x86_registerNONE for now, but could be set // if we have segment overrides MCOperand *baseReg; MCOperand *scaleAmount; MCOperand *indexReg; MCOperand *displacement; MCOperand *segmentReg; bool IndexIs512; if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { if (insn->sibBase != SIB_BASE_NONE) { switch (insn->sibBase) { #define ENTRY(x) \ case SIB_BASE_##x: \ baseReg = MCOperand_CreateReg(X86_##x); break; ALL_SIB_BASES #undef ENTRY default: //debug("Unexpected sibBase"); return true; } } else { baseReg = MCOperand_CreateReg(0); } // Check whether we are handling VSIB addressing mode for GATHER. // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and // we should use SIB_INDEX_XMM4|YMM4 for VSIB. // I don't see a way to get the correct IndexReg in readSIB: // We can tell whether it is VSIB or SIB after instruction ID is decoded, // but instruction ID may not be decoded yet when calling readSIB. uint32_t Opcode = MCInst_getOpcode(mcInst); bool IndexIs128 = (Opcode == X86_VGATHERDPDrm || Opcode == X86_VGATHERDPDYrm || Opcode == X86_VGATHERQPDrm || Opcode == X86_VGATHERDPSrm || Opcode == X86_VGATHERQPSrm || Opcode == X86_VPGATHERDQrm || Opcode == X86_VPGATHERDQYrm || Opcode == X86_VPGATHERQQrm || Opcode == X86_VPGATHERDDrm || Opcode == X86_VPGATHERQDrm); bool IndexIs256 = (Opcode == X86_VGATHERQPDYrm || Opcode == X86_VGATHERDPSYrm || Opcode == X86_VGATHERQPSYrm || Opcode == X86_VGATHERDPDZrm || Opcode == X86_VPGATHERDQZrm || Opcode == X86_VPGATHERQQYrm || Opcode == X86_VPGATHERDDYrm || Opcode == X86_VPGATHERQDYrm); IndexIs512 = (Opcode == X86_VGATHERQPDZrm || Opcode == X86_VGATHERDPSZrm || Opcode == X86_VGATHERQPSZrm || Opcode == X86_VPGATHERQQZrm || Opcode == X86_VPGATHERDDZrm || Opcode == X86_VPGATHERQDZrm); if (IndexIs128 || IndexIs256 || IndexIs512) { unsigned IndexOffset = insn->sibIndex - (insn->addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 : IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0; insn->sibIndex = (SIBIndex)(IndexBase + (insn->sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset)); } if (insn->sibIndex != SIB_INDEX_NONE) { switch (insn->sibIndex) { default: //debug("Unexpected sibIndex"); return true; #define ENTRY(x) \ case SIB_INDEX_##x: \ indexReg = MCOperand_CreateReg(X86_##x); break; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM REGS_ZMM #undef ENTRY } } else {
/// translateImmediate - Appends an immediate operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param immediate - The immediate value to append. /// @param operand - The operand, as stored in the descriptor table. /// @param insn - The internal instruction. static void translateImmediate(MCInst *mcInst, uint64_t immediate, const OperandSpecifier *operand, InternalInstruction *insn) { OperandType type; MCOperand *segmentReg; type = (OperandType)operand->type; if (type == TYPE_RELv) { //isBranch = true; //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize; switch (insn->displacementSize) { case 1: if (immediate & 0x80) immediate |= ~(0xffull); break; case 2: if (immediate & 0x8000) immediate |= ~(0xffffull); break; case 4: if (immediate & 0x80000000) immediate |= ~(0xffffffffull); break; case 8: break; default: break; } } // By default sign-extend all X86 immediates based on their encoding. else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || type == TYPE_IMM64) { uint32_t Opcode = MCInst_getOpcode(mcInst); switch (operand->encoding) { default: break; case ENCODING_IB: // Special case those X86 instructions that use the imm8 as a set of // bits, bit count, etc. and are not sign-extend. if (Opcode != X86_BLENDPSrri && Opcode != X86_BLENDPDrri && Opcode != X86_PBLENDWrri && Opcode != X86_MPSADBWrri && Opcode != X86_DPPSrri && Opcode != X86_DPPDrri && Opcode != X86_INSERTPSrr && Opcode != X86_VBLENDPSYrri && Opcode != X86_VBLENDPSYrmi && Opcode != X86_VBLENDPDYrri && Opcode != X86_VBLENDPDYrmi && Opcode != X86_VPBLENDWrri && Opcode != X86_VMPSADBWrri && Opcode != X86_VDPPSYrri && Opcode != X86_VDPPSYrmi && Opcode != X86_VDPPDrri && Opcode != X86_VINSERTPSrr && Opcode != X86_INT) if(immediate & 0x80) immediate |= ~(0xffull); break; case ENCODING_IW: if(immediate & 0x8000) immediate |= ~(0xffffull); break; case ENCODING_ID: if(immediate & 0x80000000) immediate |= ~(0xffffffffull); break; case ENCODING_IO: break; } } switch (type) { case TYPE_XMM32: case TYPE_XMM64: case TYPE_XMM128: MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_XMM0 + ((uint32_t)immediate >> 4))); return; case TYPE_XMM256: MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_YMM0 + ((uint32_t)immediate >> 4))); return; case TYPE_XMM512: MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ZMM0 + ((uint32_t)immediate >> 4))); return; case TYPE_REL8: if(immediate & 0x80) immediate |= ~(0xffull); break; case TYPE_REL32: case TYPE_REL64: if(immediate & 0x80000000) immediate |= ~(0xffffffffull); break; default: // operand is 64 bits wide. Do nothing. break; } MCInst_addOperand(mcInst, MCOperand_CreateImm(immediate)); if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { segmentReg = MCOperand_CreateReg(segmentRegnums[insn->segmentOverride]); MCInst_addOperand(mcInst, segmentReg); } }
switch (insn->sibIndex) { default: //debug("Unexpected sibIndex"); return true; #define ENTRY(x) \ case SIB_INDEX_##x: \ indexReg = MCOperand_CreateReg(X86_##x); break; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM REGS_ZMM #undef ENTRY } } else { indexReg = MCOperand_CreateReg(0); } scaleAmount = MCOperand_CreateImm(insn->sibScale); } else { switch (insn->eaBase) { case EA_BASE_NONE: if (insn->eaDisplacement == EA_DISP_NONE) { //debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); return true; } if (insn->mode == MODE_64BIT) { baseReg = MCOperand_CreateReg(X86_RIP); // Section 2.2.1.6 } else baseReg = MCOperand_CreateReg(0);