static u32 saa716x_init_ptables(struct saa716x_dmabuf *dmabuf, int channel)
{
struct saa716x_dev *saa716x = dmabuf->saa716x;
u32 config, i;
for (i = 0; i < FGPI_BUFFERS; i++)
BUG_ON((dmabuf[i].mem_ptab_phys == 0));
config = mmu_dma_cfg[channel]; /* DMACONFIGx */
SAA716x_EPWR(MMU, config, (FGPI_BUFFERS - 1));
SAA716x_EPWR(MMU, MMU_PTA0_LSB(channel), PTA_LSB(dmabuf[0].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA0_MSB(channel), PTA_MSB(dmabuf[0].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA1_LSB(channel), PTA_LSB(dmabuf[1].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA1_MSB(channel), PTA_MSB(dmabuf[1].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA2_LSB(channel), PTA_LSB(dmabuf[2].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA2_MSB(channel), PTA_MSB(dmabuf[2].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA3_LSB(channel), PTA_LSB(dmabuf[3].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA3_MSB(channel), PTA_MSB(dmabuf[3].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA4_LSB(channel), PTA_LSB(dmabuf[4].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA4_MSB(channel), PTA_MSB(dmabuf[4].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA5_LSB(channel), PTA_LSB(dmabuf[5].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA5_MSB(channel), PTA_MSB(dmabuf[5].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA6_LSB(channel), PTA_LSB(dmabuf[6].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA6_MSB(channel), PTA_MSB(dmabuf[6].mem_ptab_phys)); /* High */
SAA716x_EPWR(MMU, MMU_PTA7_LSB(channel), PTA_LSB(dmabuf[7].mem_ptab_phys)); /* Low */
SAA716x_EPWR(MMU, MMU_PTA7_MSB(channel), PTA_MSB(dmabuf[7].mem_ptab_phys)); /* High */
return 0;
}
static int saa7231_init_ptables(struct saa7231_stream *stream)
{
struct saa7231_ring *ring = stream->ring;
struct saa7231_dmabuf *dmabuf = ring->dmabuf;
struct saa7231_dev *saa7231 = dmabuf->saa7231;
int port = stream->port_id;
int ch = DMACH(port);
BUG_ON(!ring);
BUG_ON(!dmabuf);
BUG_ON(!saa7231);
dprintk(SAA7231_DEBUG, 1, "DEBUG: Initializing PORT:%d DMA_CH:%d with %d Buffers",
port,
ch,
TS2D_BUFFERS);
SAA7231_WR((TS2D_BUFFERS - 1), SAA7231_BAR0, MMU, MMU_DMA_CONFIG(ch));
SAA7231_WR(PTA_LSB(dmabuf[0].pt_phys), SAA7231_BAR0, MMU, MMU_PTA0_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[0].pt_phys), SAA7231_BAR0, MMU, MMU_PTA0_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[1].pt_phys), SAA7231_BAR0, MMU, MMU_PTA1_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[1].pt_phys), SAA7231_BAR0, MMU, MMU_PTA1_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[2].pt_phys), SAA7231_BAR0, MMU, MMU_PTA2_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[2].pt_phys), SAA7231_BAR0, MMU, MMU_PTA2_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[3].pt_phys), SAA7231_BAR0, MMU, MMU_PTA3_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[3].pt_phys), SAA7231_BAR0, MMU, MMU_PTA3_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[4].pt_phys), SAA7231_BAR0, MMU, MMU_PTA4_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[4].pt_phys), SAA7231_BAR0, MMU, MMU_PTA4_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[5].pt_phys), SAA7231_BAR0, MMU, MMU_PTA5_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[5].pt_phys), SAA7231_BAR0, MMU, MMU_PTA5_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[6].pt_phys), SAA7231_BAR0, MMU, MMU_PTA6_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[6].pt_phys), SAA7231_BAR0, MMU, MMU_PTA6_MSB(ch));
SAA7231_WR(PTA_LSB(dmabuf[7].pt_phys), SAA7231_BAR0, MMU, MMU_PTA7_LSB(ch));
SAA7231_WR(PTA_MSB(dmabuf[7].pt_phys), SAA7231_BAR0, MMU, MMU_PTA7_MSB(ch));
stream->index_w += 8;
return 0;
}