//========================[ HCLK, PCLK ]=========================== void ChangeClockDivider(int hdivn,int pdivn) { // hdivn,pdivn FCLK:HCLK:PCLK // 0,0 1:1:1 // 0,1 1:1:2 // 1,0 1:2:2 // 1,1 1:2:4 rCLKDIVN = (hdivn<<1) | pdivn; if(hdivn) MMU_SetAsyncBusMode(); else MMU_SetFastBusMode(); }
//************************[ HCLK, PCLK ]*************************** void ChangeClockDivider(int hdivn_val,int pdivn_val) { int hdivn=2, pdivn=0; // hdivn_val (FCLK:HCLK)ratio hdivn // 11 1:1 (0) // 12 1:2 (1) // 13 1:3 (3) // 14 1:4 (2) // pdivn_val (HCLK:PCLK)ratio pdivn // 11 1:1 (0) // 12 1:2 (1) switch(hdivn_val) { case 11: hdivn=0; break; case 12: hdivn=1; break; case 13: hdivn=3; break; case 16: hdivn=3; break; case 14: hdivn=2; break; case 18: hdivn=2; break; } switch(pdivn_val) { case 11: pdivn=0; break; case 12: pdivn=1; break; } //Uart_Printf("Clock division change [hdiv:%x, pdiv:%x]\n", hdivn, pdivn); rCLKDIVN = (hdivn<<1) | pdivn; //Uart_Printf("rCLKDIVN:%x]\n", rCLKDIVN); switch(hdivn_val) { case 16: // when 1, HCLK=FCLK/6. rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<8); break; case 18: // when 1, HCLK=FCLK/8. rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<9); break; } //Uart_Printf("rCAMDIVN:%x]\n", rCAMDIVN); if(hdivn!=0) MMU_SetAsyncBusMode(); else MMU_SetFastBusMode(); }