* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "msrtool.h"
int intel_pentium3_early_probe(const struct targetdef *target) {
struct cpuid_t *id = cpuid();
return ((0x6 == id->family)&((0x7 == id->model)|(0x8 == id->model)));
}
const struct msrdef intel_pentium3_early_msrs[] = {
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
{ BITS_EOT }
}},
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
{ BITS_EOT }
}},
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
{ BITS_EOT }
}},
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
{ BITS_EOT }
}},
{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
{ BITS_EOT }
}},
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
return (NULL != pci_dev_find(0x1022, 0x2090));
}
/**
* Documentation referenced:
*
* 33238G: AMD Geode(tm) CS5536 Companion Device Data Book
* http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33238G_cs5536_db.pdf
*
*/
const struct msrdef cs5536_msrs[] = {
/* 0x51400008-0x5140000f per 33238G pages 356-361 */
/* 0x51400015 per 33238G pages 365-366 */
/* 0x51400020-0x51400027 per 33238G pages 379-385 */
{ 0x51400008, MSRTYPE_RDWR, MSR2(0, 0), "DIVIL_LBAR_IRQ", "Local BAR - IRQ Mapper", {
{ 63, 15, RESERVED },
{ 48, 1, RESERVED },
{ 47, 4, "IO_MASK", "I/O Address Mask Value", PRESENT_BIN, {
{ BITVAL_EOT }
}},
{ 43, 11, RESERVED },
{ 32, 1, "LBAR_EN", "LBAR Enable", PRESENT_BIN, {
{ MSR1(0), "Disable LBAR" },
{ MSR1(1), "Enable LBAR" },
{ BITVAL_EOT }
}},
{ 31, 15, RESERVED },
{ 16, 1, RESERVED },
{ 15, 11, "BASE_ADDR", "Base Address in I/O Space", PRESENT_HEX, {
{ BITVAL_EOT }
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "msrtool.h"
int intel_pentium4_later_probe(const struct targetdef *target, const struct cpuid_t *id) {
return ((VENDOR_INTEL == id->vendor) &&
(0xf == id->family) && (
(0x3 == id->model) ||
(0x4 == id->model)
));
}
const struct msrdef intel_pentium4_later_msrs[] = {
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
{ BITS_EOT }
}},
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
{ BITS_EOT }
}},
{0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
{ BITS_EOT }
}},
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
{ BITS_EOT }
}},
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
{ BITS_EOT }
}},
{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "msrtool.h"
int k8_probe(const struct targetdef *target, const struct cpuid_t *id) {
return 0xF == id->family;
}
/*
* AMD BKDG Publication # 32559 Revision: 3.08 Issue Date: July 2007
*/
const struct msrdef k8_msrs[] = {
{ 0xC0000080, MSRTYPE_RDWR, MSR2(0, 0), "EFER Register", "Extended Feature Enable Register", {
{ 63, 32, RESERVED },
{ 31, 18, RESERVED },
{ 14, 1, "FFXSR:", "Fast FXSAVE/FRSTOR Enable", PRESENT_DEC, {
{ MSR1(0), "FXSAVE/FRSTOR disabled" },
{ MSR1(1), "FXSAVE/FRSTOR enabled" },
{ BITVAL_EOT }
}},
{ 13, 1, "LMSLE:", "Long Mode Segment Limit Enable", PRESENT_DEC, {
{ MSR1(0), "Long mode segment limit check disabled" },
{ MSR1(1), "Long mode segment limit check enabled" },
{ BITVAL_EOT }
}},
{ 12, 1, "SVME:", "SVM Enable", PRESENT_DEC, {
{ MSR1(0), "SVM features disabled" },
{ MSR1(1), "SVM features enabled" },
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "msrtool.h"
int intel_pentium4_later_probe(const struct targetdef *target, const struct cpuid_t *id) {
return ((0xf == id->family) && (
(0x3 == id->model) ||
(0x4 == id->model)
));
}
const struct msrdef intel_pentium4_later_msrs[] = {
{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
{ BITS_EOT }
}},
{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
{ BITS_EOT }
}},
{0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
{ BITS_EOT }
}},
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
{ BITS_EOT }
}},
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", {
{ BITS_EOT }
}},
{0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", {
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "msrtool.h"
int geodelx_probe(const struct targetdef *target, const struct cpuid_t *id) {
return 5 == id->family && 10 == id->model;
}
const struct msrdef geodelx_msrs[] = {
{ 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
{ 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
{ MSR1(0), "Reserved" },
{ MSR1(1), "8 MB" },
{ MSR1(2), "16 MB" },
{ MSR1(3), "32 MB" },
{ MSR1(4), "64 MB" },
{ MSR1(5), "128 MB" },
{ MSR1(6), "256 MB" },
{ MSR1(7), "512 MB" },
{ MSR1(8), "1 GB" },
{ MSR1(9), "Reserved" },
{ MSR1(10), "Reserved" },
{ MSR1(11), "Reserved" },
{ MSR1(12), "Reserved" },
{ MSR1(13), "Reserved" },
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "msrtool.h"
int intel_pentium3_probe(const struct targetdef *target, const struct cpuid_t *id) {
return ((VENDOR_INTEL == id->vendor) &&
(0x6 == id->family) && (
(0xa == id->model) ||
(0xb == id->model)
));
}
const struct msrdef intel_pentium3_msrs[] = {
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
{ BITS_EOT }
}},
{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
{ BITS_EOT }
}},
{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
{ BITS_EOT }
}},
{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
{ BITS_EOT }
}},
{0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
{ BITS_EOT }
}},
{0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", {
int main(int argc, char *argv[]) {
char c;
int ret = 1;
const struct sysdef *s;
const struct targetdef *t;
uint8_t tn, listmsrs = 0, listknown = 0, input = 0;
uint32_t addr = 0;
const char *streamfn = NULL, *difffn = NULL;
struct msr msrval = MSR2(-1, -1);
while ((c = getopt(argc, argv, "hqvrklc:m:t:a:i:s:d:")) != -1)
switch (c) {
case 'h':
syntax(argv);
return 0;
case 'q':
quiet = 1;
break;
case 'v':
++verbose;
break;
case 'r':
reserved = 1;
break;
case 'k':
listknown = 1;
break;
case 'l':
listmsrs = 1;
break;
case 'c':
cpu = atoi(optarg);
break;
case 'm':
for (s = allsystems; !SYSTEM_ISEOT(*s); s++)
if (!strcmp(s->name, optarg)) {
sys = s;
break;
}
break;
case 't':
for (t = alltargets; !TARGET_ISEOT(*t); t++)
if (!strcmp(t->name, optarg)) {
add_target(t);
break;
}
break;
case 'i':
input = 1;
addr = msraddrbyname(optarg);
optarg = strchr(optarg, '=');
if (NULL == optarg) {
fprintf(stderr, "missing value in -i argument!\n");
break;
}
if (!str2msr(++optarg, &msrval, NULL))
fprintf(stderr, "invalid value in -i argument!\n");
break;
case 's':
streamfn = optarg;
break;
case 'd':
difffn = optarg;
break;
default:
break;
}
printf_quiet("msrtool %s\n", VERSION);
pacc = pci_alloc();
if (NULL == pacc) {
fprintf(stderr, "Could not initialize PCI library! pci_alloc() failed.\n");
return 1;
}
pci_init(pacc);
pci_scan_bus(pacc);
if (!sys && !input && !listknown)
for (sys = allsystems; !SYSTEM_ISEOT(*sys); sys++) {
printf_verbose("Probing for system %s: %s\n", sys->name, sys->prettyname);
if (!sys->probe(sys))
continue;
printf_quiet("Detected system %s: %s\n", sys->name, sys->prettyname);
break;
}
if (targets)
for (tn = 0; tn < targets_found; tn++)
printf_quiet("Forced target %s: %s\n", targets[tn]->name, targets[tn]->prettyname);
else
for (t = alltargets; !TARGET_ISEOT(*t); t++) {
printf_verbose("Probing for target %s: %s\n", t->name, t->prettyname);
if (!t->probe(t))
continue;
printf_quiet("Detected target %s: %s\n", t->name, t->prettyname);
add_target(t);
}
printf_quiet("\n");
fflush(stdout);
if (listknown) {
printf("Known systems:\n");
for (s = allsystems; s->name; s++)
printf("%s: %s\n", s->name, s->prettyname);
printf("\nKnown targets:\n");
for (t = alltargets; t->name; t++) {
if (listmsrs && alltargets != t)
printf("\n");
printf("%s: %s\n", t->name, t->prettyname);
if (listmsrs)
dumpmsrdefs(t);
}
printf("\n");
return 0;
}
if (!targets_found || !targets) {
fprintf(stderr, "Unable to detect a known target; can not decode any MSRs! (Use -t to force)\n");
fprintf(stderr, "Please send a report or patch to [email protected]. Thanks for your help!\n");
fprintf(stderr, "\n");
return 1;
}
if (input) {
decodemsr(cpu, addr, msrval);
return 0;
}
if (listmsrs) {
if (streamfn)
return do_stream(streamfn, 1);
for (tn = 0; tn < targets_found; tn++) {
if (tn)
printf("\n");
dumpmsrdefs(targets[tn]);
}
printf("\n");
return 0;
}
if (streamfn)
return do_stream(streamfn, 0);
if (difffn) {
ret = do_diff(difffn);
goto done;
}
if (optind == argc) {
syntax(argv);
printf("\nNo mode or address(es) specified!\n");
goto done;
}
if (!found_system())
return 1;
if (!sys->open(cpu, SYS_RDONLY))
return 1;
for (; optind < argc; optind++) {
addr = msraddrbyname(argv[optind]);
if (!sys->rdmsr(cpu, addr, &msrval))
break;
decodemsr(cpu, addr, msrval);
}
ret = 0;
done:
sys->close(cpu);
return ret;
}
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "msrtool.h"
int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t *id) {
return ((0x6 == id->family) && (0xf == id->model));
}
const struct msrdef intel_core2_early_msrs[] = {
{ 0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
{ BITS_EOT }
}
},
{ 0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
{ BITS_EOT }
}
},
{ 0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
{ BITS_EOT }
}
},
{ 0xa8, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE0", "", {
{ BITS_EOT }
}
},