//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// GGM
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ISP_MGR_GGM_T&
ISP_MGR_GGM_T::
getInstance(ESensorDev_T const eSensorDev)
{
switch (eSensorDev)
{
case ESensorDev_Main: // Main Sensor
return ISP_MGR_GGM_DEV<ESensorDev_Main>::getInstance();
case ESensorDev_MainSecond: // Main Second Sensor
return ISP_MGR_GGM_DEV<ESensorDev_MainSecond>::getInstance();
case ESensorDev_Sub: // Sub Sensor
return ISP_MGR_GGM_DEV<ESensorDev_Sub>::getInstance();
default:
MY_ERR("eSensorDev = %d", eSensorDev);
return ISP_MGR_GGM_DEV<ESensorDev_Main>::getInstance();
}
}
static int get_runtime_ring_path_param( RingVariant_t i_ringVariant, char*& o_ringPath)
{
switch (i_ringVariant)
{
case RV_BASE:
o_ringPath = getenv("RUNTIME_BASE");
break;
case RV_RL:
o_ringPath = getenv("RUNTIME_RISK");
break;
case RV_RL2:
o_ringPath = getenv("RUNTIME_RISK2");
break;
case RV_RL3:
o_ringPath = getenv("RUNTIME_RISK3");
break;
case RV_RL4:
o_ringPath = getenv("RUNTIME_RISK4");
break;
case RV_RL5:
o_ringPath = getenv("RUNTIME_RISK5");
break;
default:
o_ringPath = NULL;
break;
}
if (o_ringPath == NULL)
{
MY_ERR("get_runtime_ring_path_param(): RUNTIME env parm for ringVariant=0x%x not set.\n",
i_ringVariant);
return INFRASTRUCT_RC_ENV_ERROR;
}
return INFRASTRUCT_RC_SUCCESS;
}
#include <iprt/asm.h>
#include <iprt/string.h>
#include <iprt/err.h>
/*********************************************************************************************************************************
* Global Variables *
*********************************************************************************************************************************/
/** Array of messages.
* The data is generated by a sed script.
*/
static const RTCOMERRMSG g_aStatusMsgs[] =
{
#define MY_ERR(_def, _desc, _val) { _desc, _def, _val }
MY_ERR("NS_OK", "Success", UINT32_C(0x00000000)),
MY_ERR("NS_ERROR_NOT_IMPLEMENTED", "Not implemented", UINT32_C(0x80004001)),
MY_ERR("NS_ERROR_NO_INTERFACE", "Interface not supported", UINT32_C(0x80004002)),
MY_ERR("NS_ERROR_INVALID_POINTER", "Invalid pointer value", UINT32_C(0x80004003)),
MY_ERR("NS_ERROR_ABORT", "Operation aborted", UINT32_C(0x80004004)),
MY_ERR("NS_ERROR_FAILURE", "Operation failed", UINT32_C(0x80004005)),
MY_ERR("NS_ERROR_CALL_FAILED", "Call to remote object failed", UINT32_C(0x800706be)),
MY_ERR("NS_ERROR_UNEXPECTED", "Unexpected error", UINT32_C(0x8000ffff)),
MY_ERR("NS_ERROR_CANNOT_CONVERT_DATA", "Cannot convert data", UINT32_C(0x80010001)),
MY_ERR("NS_ERROR_OBJECT_IS_IMMUTABLE", "Object is immutable", UINT32_C(0x80010002)),
MY_ERR("NS_ERROR_LOSS_OF_SIGNIFICANT_DATA", "Loss of significant data", UINT32_C(0x80010003)),
MY_ERR("NS_ERROR_PROXY_INVALID_IN_PARAMETER", "Cannot proxy an IN parameter", UINT32_C(0x80010010)),
MY_ERR("NS_ERROR_PROXY_INVALID_OUT_PARAMETER", "Cannot proxy an OUT parameter", UINT32_C(0x80010011)),
MY_ERR("NS_SUCCESS_LOSS_OF_INSIGNIFICANT_DATA", "Loss of insignificant data", UINT32_C(0x00010001)),
int ringid_get_properties( ChipType_t i_chipType,
uint32_t i_torMagic,
uint8_t i_torVersion,
ChipletType_t i_chipletType,
ChipletData_t** o_chipletData,
GenRingIdList** o_ringIdListCommon,
GenRingIdList** o_ringIdListInstance,
RingVariantOrder** o_ringVariantOrder,
RingProperties_t** o_ringProps,
uint8_t* o_numVariants )
{
switch (i_chipType)
{
case CT_P9N:
case CT_P9C:
case CT_P9A:
if ( i_torMagic == TOR_MAGIC_SBE ||
i_torMagic == TOR_MAGIC_OVRD ||
i_torMagic == TOR_MAGIC_OVLY )
{
P9_RID::ringid_get_chiplet_properties(
i_chipletType,
o_chipletData,
o_ringIdListCommon,
o_ringIdListInstance,
o_ringVariantOrder,
o_numVariants);
if ( i_torVersion < 7 &&
(i_chipletType == P9_RID::EQ_TYPE || i_chipletType == P9_RID::EC_TYPE) )
{
*o_numVariants = *o_numVariants - 3;
}
if ( i_torMagic == TOR_MAGIC_OVRD ||
i_torMagic == TOR_MAGIC_OVLY )
{
*o_numVariants = 1;
}
}
else if ( i_torMagic == TOR_MAGIC_CME )
{
*o_chipletData = (ChipletData_t*)&P9_RID::EC::g_chipletData;
*o_ringIdListCommon = (GenRingIdList*)P9_RID::EC::RING_ID_LIST_COMMON;
*o_ringIdListInstance = (GenRingIdList*)P9_RID::EC::RING_ID_LIST_INSTANCE;
*o_ringVariantOrder = (RingVariantOrder*)P9_RID::EC::RING_VARIANT_ORDER;
*o_numVariants = P9_RID::EC::g_chipletData.iv_num_common_ring_variants;
if (i_torVersion < 7)
{
*o_numVariants = *o_numVariants - 3;
}
}
else if ( i_torMagic == TOR_MAGIC_SGPE )
{
*o_chipletData = (ChipletData_t*)&P9_RID::EQ::g_chipletData;
*o_ringIdListCommon = (GenRingIdList*)P9_RID::EQ::RING_ID_LIST_COMMON;
*o_ringIdListInstance = (GenRingIdList*)P9_RID::EQ::RING_ID_LIST_INSTANCE;
*o_ringVariantOrder = (RingVariantOrder*)P9_RID::EQ::RING_VARIANT_ORDER;
*o_numVariants = P9_RID::EQ::g_chipletData.iv_num_common_ring_variants;
if (i_torVersion < 7)
{
*o_numVariants = *o_numVariants - 3;
}
}
else
{
MY_ERR("Invalid torMagic (=0x%08x) for chipType=CT_P9x=%d\n", i_torMagic, i_chipType);
return TOR_INVALID_MAGIC_NUMBER;
}
*o_ringProps = (RingProperties_t*)P9_RID::RING_PROPERTIES;
break;
case CT_CEN:
if ( i_torMagic == TOR_MAGIC_CEN ||
i_torMagic == TOR_MAGIC_OVRD )
{
CEN_RID::ringid_get_chiplet_properties(
i_chipletType,
o_chipletData,
o_ringIdListCommon,
o_ringIdListInstance,
o_ringVariantOrder,
o_numVariants);
if ( i_torMagic == TOR_MAGIC_OVRD)
{
*o_numVariants = 1;
}
}
else
{
MY_ERR("Invalid torMagic (=0x%08x) for chipType=CT_CEN\n", i_torMagic);
return TOR_INVALID_MAGIC_NUMBER;
}
*o_ringProps = (RingProperties_t*)CEN_RID::RING_PROPERTIES;
break;
default:
MY_ERR("Invalid chipType (=0x%02x)\n", i_chipType);
return TOR_INVALID_CHIPTYPE;
}
return TOR_SUCCESS;
}
int ringid_get_raw_ring_file_path( uint32_t i_magic,
RingVariant_t i_ringVariant,
char* io_ringPath )
{
int rc = INFRASTRUCT_RC_SUCCESS;
char* l_ringDir = NULL;
do
{
if ( i_magic == TOR_MAGIC_SBE )
{
if ( i_ringVariant == RV_BASE ||
i_ringVariant == RV_CC ||
i_ringVariant == RV_RL )
{
rc = get_ipl_ring_path_param(i_ringVariant, l_ringDir);
}
else if ( i_ringVariant == RV_RL2 ||
i_ringVariant == RV_RL3 ||
i_ringVariant == RV_RL4 ||
i_ringVariant == RV_RL5 )
{
// No IPL rings for these variants
rc = TOR_NO_RINGS_FOR_VARIANT;
}
else
{
MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n",
i_ringVariant, i_magic);
rc = TOR_INVALID_VARIANT;
}
if (rc)
{
break;
}
strcat(io_ringPath, l_ringDir);
strcat(io_ringPath, "/");
}
else if ( i_magic == TOR_MAGIC_CME ||
i_magic == TOR_MAGIC_SGPE )
{
if ( i_ringVariant == RV_BASE ||
i_ringVariant == RV_RL ||
i_ringVariant == RV_RL2 ||
i_ringVariant == RV_RL3 ||
i_ringVariant == RV_RL4 ||
i_ringVariant == RV_RL5 )
{
rc = get_runtime_ring_path_param(i_ringVariant, l_ringDir);
}
else if ( i_ringVariant == RV_CC )
{
// No Runtime rings for this variant
rc = TOR_NO_RINGS_FOR_VARIANT;
}
else
{
MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n",
i_ringVariant, i_magic);
rc = TOR_INVALID_VARIANT;
}
if (rc)
{
break;
}
strcat(io_ringPath, l_ringDir);
strcat(io_ringPath, "/");
}
else if ( i_magic == TOR_MAGIC_CEN )
{
if ( i_ringVariant == RV_BASE ||
i_ringVariant == RV_RL )
{
rc = get_ipl_ring_path_param(i_ringVariant, l_ringDir);
}
else
{
MY_ERR("Invalid ringVariant(=%d) for TOR magic=0x%08x\n",
i_ringVariant, i_magic);
rc = TOR_INVALID_VARIANT;
}
if (rc)
{
break;
}
strcat(io_ringPath, l_ringDir);
strcat(io_ringPath, "/");
}
else if ( i_magic == TOR_MAGIC_OVRD ||
i_magic == TOR_MAGIC_OVLY )
{
// Path already fully qualified. Return io_ringPath as is.
}
else
{
MY_ERR("Unsupported value of TOR magic(=0x%X)\n", i_magic);
rc = TOR_INVALID_MAGIC_NUMBER;
}
}
while(0);
return rc;
}
MINT32 CctImp::init(MINT32 sensorType)
{
MUINT32 sen_id;
MINT32 err = CCTIF_NO_ERROR;
IspDrv* pisp_drv = m_cctctrl_prop.isp_prop.m_pispdrv;
NvramDrvBase* pnvram_drv = m_cctctrl_prop.nvram_prop.m_pnvramdrv;
NSNvram::BufIF<NVRAM_CAMERA_ISP_PARAM_STRUCT>** pbuf_isp = &m_cctctrl_prop.nvram_prop.pbufIf_isp;
NSNvram::BufIF<NVRAM_CAMERA_SHADING_STRUCT>** pbuf_shd = &m_cctctrl_prop.nvram_prop.pbufIf_shd;
NSNvram::BufIF<NVRAM_CAMERA_3A_STRUCT>** pbuf_3a = &m_cctctrl_prop.nvram_prop.pbufIf_3a; //Yosen
NSNvram::BufIF<NVRAM_LENS_PARA_STRUCT>** pbuf_ln = &m_cctctrl_prop.nvram_prop.pbufIf_ln; //Yosen
/*
* SENSOR INIT
*/
mSensorDev = sensorType;
if(!m_pSensorHalObj) {
MY_ERR("[CctImp::init] m_pSensorHalObj != NULL before init()\n");
return -1;
}
m_pSensorHalObj->init();
err = m_pSensorHalObj->sendCommand((halSensorDev_e)sensorType,
SENSOR_CMD_SET_SENSOR_DEV,
0,
0,
0);
if (err != SENSOR_NO_ERROR) {
MY_ERR("[CctImp::init] set sensor dev error\n");
return -1;
}
err = m_pSensorHalObj->sendCommand((halSensorDev_e)sensorType, SENSOR_CMD_GET_SENSOR_ID, (MINT32)&sen_id);
if (err != SENSOR_NO_ERROR) {
MY_ERR("[CctImp::init] get sensor id error\n");
return -1;
}
m_cctctrl_prop.sen_prop.m_sen_id = sen_id;
m_cctctrl_prop.sen_prop.m_sen_type = (CAMERA_DUAL_CAMERA_SENSOR_ENUM)sensorType;
MY_LOG("[CctImp::init] sen_id = %d\n", sen_id); //Yosen
MY_LOG("[CctImp::init] sensorType = %d\n", sensorType); //Yosen
/*
* ISP INIT
*/
if(!pisp_drv) {
MY_ERR("[CctImp::init] m_pispdrv == NULL before init()\n");
return -1;
}
pisp_drv->init();
/*
* NVRAM INIT
*/
if(!pnvram_drv) {
MY_ERR("[CctImp::init] pnvram_drv == NULL before init()\n");
return -1;
}
*pbuf_isp = pnvram_drv->getBufIF<NVRAM_CAMERA_ISP_PARAM_STRUCT>();
*pbuf_shd = pnvram_drv->getBufIF<NVRAM_CAMERA_SHADING_STRUCT>();
*pbuf_3a = pnvram_drv->getBufIF<NVRAM_CAMERA_3A_STRUCT>(); //Yosen
*pbuf_ln = pnvram_drv->getBufIF<NVRAM_LENS_PARA_STRUCT>(); //Yosen
/*
* CCT CTRL INIT
*/
m_pCctCtrl = CctCtrl::createInstance(&m_cctctrl_prop);
if (!m_pCctCtrl )
{
MY_ERR("[CctImp::init] m_pCctCtrl == NULL\n");
return -1;
}
return 0;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MBOOL
IspDebug::
dumpIspDebugMessage()
{
MY_LOG_IF("%s()\n", __FUNCTION__);
if (!m_pIspReg) {
MY_ERR("m_pIspReg is NULL\n");
return MFALSE;
}
// DMA status check
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_DMA_INT, AAO_DONE_ST) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_DMA_INT, AAO_DONE_ST));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, AA_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, AA_EN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_DMA_EN, AAO_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_DMA_EN, AAO_EN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_MUX_SEL, AA_SEL_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_MUX_SEL, AA_SEL_EN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_MUX_SEL, AA_SEL) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_MUX_SEL, AA_SEL));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AAO_OFST_ADDR, OFFSET_ADDR) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AAO_OFST_ADDR, OFFSET_ADDR));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AAO_XSIZE, XSIZE) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AAO_XSIZE, XSIZE));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AAO_YSIZE, YSIZE) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AAO_YSIZE, YSIZE));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AAO_STRIDE, BUS_SIZE) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AAO_STRIDE, BUS_SIZE));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST0_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST0_EN));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST1_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST1_EN));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST2_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST2_EN));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST3_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_HST_CTL, AE_HST3_EN));
#if 0
// CAM_AWB_WIN_ORG
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_ORG, AWB_WIN_ORIGIN_X) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_ORG, AWB_W_ORIGIN_X));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_ORG, AWB_WIN_ORIGIN_Y) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_ORG, AWB_W_ORIGIN_Y));
// CAM_AWB_WIN_SIZE
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_SIZE, AWB_WIN_SIZE_X) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_SIZE, AWB_W_SIZE_X));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_SIZE, AWB_WIN_SIZE_Y) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_SIZE, AWB_W_SIZE_Y));
// CAM_AWB_WIN_PITCH
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_PITCH, AWB_WIN_PITCH_X) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_PITCH, AWB_W_PITCH_X));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_PITCH, AWB_WIN_PITCH_Y) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_PITCH, AWB_W_PITCH_Y));
// CAM_AWB_WIN_NUM
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_NUM, AWB_WIN_NUM_X) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_NUM, AWB_W_NUM_X));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_NUM, AWB_WIN_NUM_Y) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_WIN_NUM, AWB_W_NUM_Y));
// CAM_AWB_RAWPREGAIN1_0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWPREGAIN1_0, RAWPREGAIN1_R) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWPREGAIN1_0, AWB_GAIN1_R));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWPREGAIN1_0, RAWPREGAIN1_G) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWPREGAIN1_0, AWB_GAIN1_G));
// CAM_AWB_RAWPREGAIN1_1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWPREGAIN1_1, RAWPREGAIN1_B) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWPREGAIN1_1, AWB_GAIN1_B));
// CAM_AWB_RAWLIMIT1_0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWLIMIT1_0, RAWLIMIT1_R) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWLIMIT1_0, AWB_LIMIT1_R));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWLIMIT1_0, RAWLIMIT1_G) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWLIMIT1_0, AWB_LIMIT1_G));
// CAM_AWB_RAWLIMIT1_1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWLIMIT1_1, RAWLIMIT1_B) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_RAWLIMIT1_1, AWB_LIMIT1_B));
// CAM_AWB_LOW_THR
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_LOW_THR, AWB_LOW_THR0) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_LOW_THR, AWB_LOW_THR0));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_LOW_THR, AWB_LOW_THR1) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_LOW_THR, AWB_LOW_THR1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_LOW_THR, AWB_LOW_THR2) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_LOW_THR, AWB_LOW_THR2));
// CAM_AWB_HI_THR
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_HI_THR, AWB_HI_THR0) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_HI_THR, AWB_HI_THR0));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_HI_THR, AWB_HI_THR1) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_HI_THR, AWB_HI_THR1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_HI_THR, AWB_HI_THR2) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_HI_THR, AWB_HI_THR2));
// CAM_AWB_PIXEL_CNT0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_PIXEL_CNT0, PIXEL_CNT0) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_PIXEL_CNT0, PIXEL_CNT0));
// CAM_AWB_PIXEL_CNT1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_PIXEL_CNT1, PIXEL_CNT1) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_PIXEL_CNT1, PIXEL_CNT1));
// CAM_AWB_PIXEL_CNT2
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_PIXEL_CNT2, PIXEL_CNT2) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_PIXEL_CNT2, PIXEL_CNT2));
// CAM_AWB_ERR_THR
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_ERR_THR, AWB_ERR_THR) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_ERR_THR, AWB_ERR_THR));
// CAM_AWB_ROT
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_ROT, AWB_COS) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_ROT, AWB_C));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_ROT, AWB_SIN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_ROT, AWB_S));
// CAM_AWB_L0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_X, AWB_L0_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_X, AWB_L0_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_X, AWB_L0_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_X, AWB_L0_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_Y, AWB_L0_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_Y, AWB_L0_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_Y, AWB_L0_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L0_Y, AWB_L0_Y_UP));
// CAM_AWB_L1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_X, AWB_L1_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_X, AWB_L1_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_X, AWB_L1_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_X, AWB_L1_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_Y, AWB_L1_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_Y, AWB_L1_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_Y, AWB_L1_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L1_Y, AWB_L1_Y_UP));
// CAM_AWB_L2
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_X, AWB_L2_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_X, AWB_L2_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_X, AWB_L2_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_X, AWB_L2_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_Y, AWB_L2_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_Y, AWB_L2_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_Y, AWB_L2_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L2_Y, AWB_L2_Y_UP));
// CAM_AWB_L3
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_X, AWB_L3_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_X, AWB_L3_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_X, AWB_L3_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_X, AWB_L3_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_Y, AWB_L3_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_Y, AWB_L3_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_Y, AWB_L3_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L3_Y, AWB_L3_Y_UP));
// CAM_AWB_L4
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_X, AWB_L4_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_X, AWB_L4_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_X, AWB_L4_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_X, AWB_L4_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_Y, AWB_L4_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_Y, AWB_L4_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_Y, AWB_L4_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L4_Y, AWB_L4_Y_UP));
// CAM_AWB_L5
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_X, AWB_L5_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_X, AWB_L5_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_X, AWB_L5_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_X, AWB_L5_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_Y, AWB_L5_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_Y, AWB_L5_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_Y, AWB_L5_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L5_Y, AWB_L5_Y_UP));
// CAM_AWB_L6
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_X, AWB_L6_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_X, AWB_L6_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_X, AWB_L6_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_X, AWB_L6_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_Y, AWB_L6_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_Y, AWB_L6_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_Y, AWB_L6_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L6_Y, AWB_L6_Y_UP));
// CAM_AWB_L7
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_X, AWB_L7_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_X, AWB_L7_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_X, AWB_L7_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_X, AWB_L7_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_Y, AWB_L7_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_Y, AWB_L7_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_Y, AWB_L7_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L7_Y, AWB_L7_Y_UP));
// CAM_AWB_L8
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_X, AWB_L8_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_X, AWB_L8_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_X, AWB_L8_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_X, AWB_L8_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_Y, AWB_L8_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_Y, AWB_L8_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_Y, AWB_L8_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L8_Y, AWB_L8_Y_UP));
// CAM_AWB_L9
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_X, AWB_L9_X_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_X, AWB_L9_X_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_X, AWB_L9_X_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_X, AWB_L9_X_UP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_Y, AWB_L9_Y_LOW) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_Y, AWB_L9_Y_LOW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_Y, AWB_L9_Y_UP) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AWB_L9_Y, AWB_L9_Y_UP));
// CAM_AE_RAWPREGAIN2_0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_RAWPREGAIN2_0, RAWPREGAIN2_R) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_RAWPREGAIN2_0, AE_GAIN2_R));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_RAWPREGAIN2_0, RAWPREGAIN2_G) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_RAWPREGAIN2_0, AE_GAIN2_G));
// CAM_AE_RAWPREGAIN2_1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_AE_RAWPREGAIN2_1, RAWPREGAIN2_B) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_AE_RAWPREGAIN2_1, AE_GAIN2_B));
#endif
// OBC
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, OB_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, OB_EN));
#if 1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST0, OBOFFSET0) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST0, OBOFFSET0));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST1, OBOFFSET1) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST1, OBOFFSET1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST2, OBOFFSET2) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST2, OBOFFSET2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST3, OBOFFSET3) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_OFFST3, OBOFFSET3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN0, OBGAIN0) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN0, OBGAIN0));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN1, OBGAIN1) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN1, OBGAIN1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN2, OBGAIN2) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN2, OBGAIN2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN3, OBGAIN3) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_OBC_GAIN3, OBGAIN3));
#endif
// BPC/NR1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, BNR_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, BNR_EN));
#if 0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CON) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CON));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_4) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_4));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_5) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_5));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_6) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD1_6));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD2_1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD2_1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD2_2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD2_2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD2_3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD2_3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_CD0) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_CD0));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_DET) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_DET));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_COR) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_COR));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_TBLI1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_TBLI1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_BPC_TBLI2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_BPC_TBLI2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR1_CON) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR1_CON));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR1_CT_CON) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR1_CT_CON));
#endif
// LSC
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, LSC_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, LSC_EN));
// PGN
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, PGN_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, PGN_EN));
#if 1
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU01, PGN_CH0_SATU) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU01, PGN_CH0_SATU));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU01, PGN_CH1_SATU) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU01, PGN_CH1_SATU));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU23, PGN_CH2_SATU) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU23, PGN_CH2_SATU));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU23, PGN_CH3_SATU) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_SATU23, PGN_CH3_SATU));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN01, PGN_CH0_GAIN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN01, PGN_CH0_GAIN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN01, PGN_CH1_GAIN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN01, PGN_CH1_GAIN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN23, PGN_CH2_GAIN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN23, PGN_CH2_GAIN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN23, PGN_CH3_GAIN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_GAIN23, PGN_CH3_GAIN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS01, PGN_CH0_OFFS) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS01, PGN_CH0_OFFS));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS01, PGN_CH1_OFFS) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS01, PGN_CH1_OFFS));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS23, PGN_CH2_OFFS) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS23, PGN_CH2_OFFS));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS23, PGN_CH3_OFFS) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_PGN_OFFS23, PGN_CH3_OFFS));
#endif
// CFA
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, CFA_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, CFA_EN));
#if 0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_BYPASS) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_BYPASS));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_ED_F) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_ED_F));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_ED_NYQ) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_ED_NYQ));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_ED_STEP) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_ED_STEP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_RGB_HF) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_RGB_HF));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_BW) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_BW));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F1_ACT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F1_ACT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F2_ACT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F2_ACT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F3_ACT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F3_ACT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F4_ACT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F4_ACT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F1_L) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F1_L));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F2_L) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F2_L));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F3_L) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F3_L));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_F4_L) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_F4_L));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_HF_RB) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_HF_RB));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_HF_GAIN) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_HF_GAIN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_HF_COMP) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_HF_COMP));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_HF_CORING_TH) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_HF_CORING_TH));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_ACT_LUT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_ACT_LUT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_SPARE) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_SPARE));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CFA_BB) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CFA_BB));
#endif
// CCM
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, G2G_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, G2G_EN));
#if 1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV0A, G2G_CNV_00) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV0A, G2G_CNV_00));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV0A, G2G_CNV_01) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV0A, G2G_CNV_01));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV0B, G2G_CNV_02) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV0B, G2G_CNV_02));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV1A, G2G_CNV_10) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV1A, G2G_CNV_10));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV1A, G2G_CNV_11) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV1A, G2G_CNV_11));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV1B, G2G_CNV_12) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV1B, G2G_CNV_12));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV2A, G2G_CNV_20) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV2A, G2G_CNV_20));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV2A, G2G_CNV_21) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV2A, G2G_CNV_21));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV2B, G2G_CNV_22) = 0x%8x\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_CONV2B, G2G_CNV_22));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_G2G_ACC, G2G_ACC) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_G2G_ACC, G2G_ACC));
#endif
// GGM
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, GGM_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN1, GGM_EN));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_GGM_CTRL, GAMMA_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_GGM_CTRL, GAMMA_EN));
#if 0
//for (MINT32 i = 0; i < 144; i++) {
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_GGM_RB_GMT[%d]) = 0x%8x\n", i, ISP_READ_REG(m_pIspReg , CAM_GGM_RB_GMT[i]));
//MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_GGM_G_GMT[%d]) = 0x%8x\n", i, ISP_READ_REG(m_pIspReg , CAM_GGM_G_GMT[i]));
//}
#endif
// G2C
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, G2C_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, G2C_EN));
#if 1
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_0A) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_0A));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_0B) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_0B));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_1A) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_1A));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_1B) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_1B));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_2A) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_2A));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_2B) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_G2C_CONV_2B));
#endif
// NBC
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, NBC_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, NBC_EN));
#if 0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_CON1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_CON1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_CON2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_CON2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_CON3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_CON3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_YAD1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_YAD1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_YAD2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_YAD2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_4LUT1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_4LUT1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_4LUT2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_4LUT2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_4LUT3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_4LUT3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_PTY) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_PTY));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_CAD) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_CAD));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_PTC) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_PTC));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_LCE1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_LCE1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_LCE2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_LCE2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_HP1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_HP1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_HP2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_HP2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_HP3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_HP3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_ACTY) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_ACTY));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_ANR_ACTC) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_ANR_ACTC));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CCR_CON) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CCR_CON));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CCR_YLUT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CCR_YLUT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CCR_UVLUT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CCR_UVLUT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_CCR_YLUT2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_CCR_YLUT2));
#endif
// PCA
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, PCA_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, PCA_EN));
#if 0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_PCA_CON1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_PCA_CON1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_PCA_CON2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_PCA_CON2));
for (MINT32 i = 0; i < 179; i++) {
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_PCA_TBL[%d]) = 0x%8x\n", i, ISP_READ_REG(m_pIspReg , CAM_PCA_TBL[i]));
}
#endif
// SEEE
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, SEEE_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, SEEE_EN));
#if 0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_SRK_CTRL) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_SRK_CTRL));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_CLIP_CTRL) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_CLIP_CTRL));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_HP_CTRL1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_HP_CTRL1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_HP_CTRL2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_HP_CTRL2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL4) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL4));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL5) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL5));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL6) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL6));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL7) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_ED_CTRL7));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_Y_CTRL) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_Y_CTRL));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EDGE_CTRL3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_SPECIAL_CTRL) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_SPECIAL_CTRL));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_CORE_CTRL1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_CORE_CTRL1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_CORE_CTRL2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_CORE_CTRL2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK4) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK4));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK5) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_SEEE_EE_LINK5));
#endif
// NR3D
MY_LOG_IF(m_bDebugEnable,"ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, NR3D_EN) = %d\n", ISP_READ_BITS(m_pIspReg , CAM_CTL_EN2, NR3D_EN));
#if 0
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_BLEND) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_BLEND));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_SKIP_KEY) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_SKIP_KEY));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_FBCNT_OFF) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_FBCNT_OFF));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_FBCNT_SIZ) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_FBCNT_SIZ));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_FB_COUNT) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_FB_COUNT));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_CPX) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_CPX));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_Y_CON1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_Y_CON1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_Y_CON2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_Y_CON2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_Y_CON3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_Y_CON3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_U_CON1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_U_CON1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_U_CON2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_U_CON2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_U_CON3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_U_CON3));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_V_CON1) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_V_CON1));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_V_CON2) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_V_CON2));
MY_LOG_IF(m_bDebugEnable,"ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_V_CON3) = 0x%8x\n", ISP_READ_REG(m_pIspReg , CAM_NR3D_LIMIT_V_CON3));
#endif
return MTRUE;
}
/*
// io_image - pointer to SLW image
// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
// i_regName - unswizzled enum SPR value (NOT a name)
// i_regData - data to write
// i_coreIndex - core ID = [0:15]
// i_threadIndex - thread to operate on = [0:7].
*/
uint32_t p8_pore_gen_cpureg_fixed( void *io_image,
uint8_t i_modeBuild,
uint32_t i_regName,
uint64_t i_regData,
uint32_t i_coreId,
uint32_t i_threadId)
{
uint32_t rc=0, rcLoc=0, iCount=0;
int i=0, iReg=-1;
uint64_t xipSlwRamSection;
void *hostSlwRamSection;
void *hostSlwSectionFixed;
uint64_t xipRamTableThis;
void *hostRamVector;
void *hostRamTableThis=NULL;
void *hostRamEntryThis=NULL, *hostRamEntryNext=NULL;
uint8_t bNewTable=0, bFound=0;
uint8_t bEntryEnd=1, headerType=0;
SbeXipSection xipSection;
SbeXipItem xipTocItem;
RamTableEntry ramEntryThis, *ramEntryNext;
uint32_t sprSwiz=0;
uint8_t bReplaceEntry=0;
uint32_t headerNext=0;
uint32_t instrNext=0;
// -------------------------------------------------------------------------
// Validate Ramming parameters.
//
// ...check mode build
if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE) {
MY_ERR("modeBuild=%i invalid. Valid range is [0;%i].",
i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE);
rcLoc = 1;
}
// ...check register value
bFound = 0;
for (i=0;i<SLW_SPR_REGS_SIZE;i++) {
if (i_regName==SLW_SPR_REGS[i].value) {
bFound = 1;
iReg = i;
break;
}
}
if (!bFound) {
MY_ERR("Register value = %i is not supported.\n",i_regName);
MY_ERR("The following registers are supported:\n");
for (i=0;i<SLW_SPR_REGS_SIZE;i++)
MY_ERR("\t(%s,%i)\n",SLW_SPR_REGS[i].name,SLW_SPR_REGS[i].value);
rcLoc = 1;
}
// ...check core ID
if (i_coreId>=SLW_MAX_CORES) {
MY_ERR("Core ID = %i is not within valid range of [0;%i]\n",i_coreId,SLW_MAX_CORES-1);
rcLoc = 1;
}
// ...check thread ID
// - ensure it's zero if SPR is not thread scoped, i.e. if SPR is core scoped.
// - error out if threadId exceed max num of threads.
if (i_regName!=P8_SPR_HSPRG0 && i_regName!=P8_SPR_LPCR && i_regName!=P8_MSR_MSR) {
i_threadId = 0;
}
if (i_threadId>=SLW_CORE_THREADS) {
MY_ERR("Thread ID = %i is not within valid range of [0;%i]\n",i_threadId,SLW_CORE_THREADS-1);
rcLoc = 1;
}
if (rcLoc)
return IMGBUILD_ERR_RAM_INVALID_PARM;
rcLoc = 0;
// -------------------------------------------------------------------------
// Check slw section location and size. (Mainly needed for fixed image.)
//
if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image.
hostSlwSectionFixed = (void*)( (uintptr_t)io_image +
FIXED_SLW_IMAGE_SIZE -
FIXED_FFDC_SECTION_SIZE -
FIXED_SLW_SECTION_SIZE );
// Even though we shouldn't call this api during a rebuild, it should be
// safe to do so in this particular case since none of the info requested
// is supposed to be moved during a rebuild.
rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
if (rc) {
MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
return IMGBUILD_ERR_GET_SECTION;
}
hostSlwRamSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
if (hostSlwSectionFixed!=hostSlwRamSection) {
MY_ERR("hostSlwSectionFixed != hostSlwRamSection(from image api).\n");
return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
}
else {
MY_INF("hostSlwSectionFixed == hostSlwRamSection(from image api).\n");
}
}
else { // SRAM non-fixed image.
rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
if (rc) {
MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
return IMGBUILD_ERR_GET_SECTION;
}
hostSlwRamSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
sbe_xip_host2pore( io_image, hostSlwRamSection, &xipSlwRamSection);
}
// -------------------------------------------------------------------------
// Cross check SPR register and table defines
//
if (SLW_SPR_REGS_SIZE!=(SLW_MAX_CPUREGS_CORE+SLW_MAX_CPUREGS_THREADS)) {
MY_ERR("Defines in *.H header file not in sync.\n");
return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
}
if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE) {
MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n");
MY_ERR("Check code or image version.\n");
return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
}
// -------------------------------------------------------------------------
// Summarize parameters and checking results.
//
MY_INF("Input parameter checks - OK\n");
MY_INF("\tMode build= %i\n",i_modeBuild);
MY_INF("\tRegister = (%s,%i)\n",SLW_SPR_REGS[iReg].name,SLW_SPR_REGS[iReg].value);
MY_INF("\tCore ID = %i\n",i_coreId);
MY_INF("\tThread ID = %i\n",i_threadId);
MY_INF("Image validation and size checks - OK\n");
MY_INF("\tSLW section size= %i\n",xipSection.iv_size);
// -------------------------------------------------------------------------
// Locate RAM vector and locate RAM table associated with "This" core ID.
//
if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image.
hostRamTableThis = (void*)( (uintptr_t)io_image +
FIXED_SLW_IMAGE_SIZE -
FIXED_FFDC_SECTION_SIZE -
FIXED_SLW_SECTION_SIZE +
SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
if (*(uintptr_t*)hostRamTableThis) { // Table content NOT empty.
bNewTable = 0; // So, NOT new table.
}
else { // Table content empty.
bNewTable = 1; // So, new table.
}
}
else { // SRAM non-fixed image.
rc = sbe_xip_find( io_image, SLW_HOST_REG_VECTOR_TOC_NAME, &xipTocItem);
if (rc) {
MY_ERR("Probably invalid key word for SLW_HOST_REG_VECTOR_TOC_NAME.\n");
return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
}
sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostRamVector);
xipRamTableThis = myRev64(*((uint64_t*)hostRamVector + i_coreId));
if (xipRamTableThis) {
sbe_xip_pore2host( io_image, xipRamTableThis, &hostRamTableThis);
bNewTable = 0;
}
else {
hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection +
SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
bNewTable = 1;
}
}
// -------------------------------------------------------------------------
// Create most of the RAM entry, so it can be used to find a potential existing entry to
// replace. Postpone decision about bEntryEnd and assume its zero for now (not end).
//
if (i_regName==P8_MSR_MSR) {
// ...make the MSR header
headerType = 0x1; // MTMSRD header.
ramEntryThis.header = ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) |
( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
// ...make the MSR instr
ramEntryThis.instr = RAM_MTMSRD_INSTR_TEMPL_C;
}
else {
// ...make the SPR header
headerType = 0x0; // MTSPR header.
ramEntryThis.header = ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) |
( i_regName << RAM_HEADER_SPRN_START_C & RAM_HEADER_SPRN_MASK_C ) |
( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
// ...make the SPR instr
sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5;
if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled) {
MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n");
MY_ERR("\tsprSwiz (on-the-fly-calc)=%i\n",sprSwiz);
MY_ERR("\tSLW_SPR_REGS[%i].swizzled=%i\n",iReg,SLW_SPR_REGS[iReg].swizzled);
return IMGBUILD_ERR_RAM_CODE;
}
ramEntryThis.instr = RAM_MTSPR_INSTR_TEMPL_C | ( ( sprSwiz<<RAM_MTSPR_SPR_START_C ) & RAM_MTSPR_SPR_MASK_C );
}
// ...make the data
ramEntryThis.data = i_regData;
// -------------------------------------------------------------------------
// Determine insertion point of new RAM entry, hostRamEntryThis. The possibilities are:
// - New table => First entry
// - Existing Ram entry => Replace said entry
// - Existing table, new Ram entry => Last entry
//
bReplaceEntry = 0;
if (bNewTable) {
// Append to beginning of agreed upon static Ram table position for this coreId.
bEntryEnd = 1;
ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) |
ramEntryThis.header;
hostRamEntryThis = hostRamTableThis;
if (i_modeBuild==P8_SLW_MODEBUILD_SRAM) {
// Update RAM vector (since it is currently NULL)
*((uint64_t*)hostRamVector + i_coreId) =
myRev64( xipSlwRamSection + SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
}
}
else {
// Append at end of existing Ram table for this coreId
// or
// Replace an existing Ram entry
hostRamEntryNext = hostRamTableThis;
ramEntryNext = (RamTableEntry*)hostRamEntryNext;
headerNext = myRev32(ramEntryNext->header);
instrNext = myRev32(ramEntryNext->instr);
iCount = 1;
// Examine all entries, except last entry.
while ((headerNext & RAM_HEADER_END_MASK_C)==0 && bReplaceEntry==0) {
if (iCount>=SLW_MAX_CPUREGS_OPS) {
MY_ERR("Bad table! Header end bit not found and RAM table full (=%i entries).\n",SLW_MAX_CPUREGS_OPS);
return IMGBUILD_ERR_RAM_TABLE_END_NOT_FOUND;
}
if (ramEntryThis.header==headerNext && ramEntryThis.instr==instrNext) {
// Its a replacement. Stop searching. Go do the replacement.
bReplaceEntry = 1;
hostRamEntryThis = hostRamEntryNext;
}
else {
hostRamEntryNext = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY);
ramEntryNext = (RamTableEntry*)hostRamEntryNext;
headerNext = myRev32(ramEntryNext->header);
instrNext = myRev32(ramEntryNext->instr);
iCount++;
}
}
if (bReplaceEntry==0) {
// Examine the last entry.
if (headerNext & RAM_HEADER_END_MASK_C) {
// Now we know for sure that our new Ram entry will also be the last, either as a
// replace or append. So put the end bit into the new entry.
bEntryEnd = 1;
ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) |
ramEntryThis.header;
// Determine if to replace or append.
if (ramEntryThis.header==headerNext && ramEntryThis.instr==instrNext) {
// Its a replacement. And it would be legal to replace the very last Ram in a completely full table.
if (iCount<=SLW_MAX_CPUREGS_OPS) {
bReplaceEntry = 1;
hostRamEntryThis = hostRamEntryNext;
}
else {
MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS);
return IMGBUILD_ERR_RAM_TABLE_FULL;
}
}
else {
// Its an append. Make sure there's room for one more Ram entry.
if (iCount<SLW_MAX_CPUREGS_OPS) {
// Zero out the end bit in last entrys header (which will now be 2nd last).
ramEntryNext->header = ramEntryNext->header & myRev32(~RAM_HEADER_END_MASK_C);
hostRamEntryThis = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY);
}
else {
MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS);
return IMGBUILD_ERR_RAM_TABLE_FULL;
}
}
}
else {
MY_ERR("We should never get here. Check code. Dumping data:\n");
MY_ERR("myRev32(ramEntryNext->header) = 0x%08x\n",myRev32(ramEntryNext->header));
MY_ERR("RAM_HEADER_END_MASK_C = 0x%08x\n",RAM_HEADER_END_MASK_C);
return IMGBUILD_ERR_RAM_CODE;
}
}
}
// Summarize new table entry data
MY_INF("New table entry data (host format):\n");
MY_INF("\theader = 0x%08x\n",ramEntryThis.header);
MY_INF("\tinstr = 0x%08x\n",ramEntryThis.instr);
MY_INF("\tdata = 0x%016llx\n",ramEntryThis.data);
// -------------------------------------------------------------------------
// Insert the new RAM entry into the table in BE format.
//
ramEntryNext = (RamTableEntry*)hostRamEntryThis;
// ...some redundant checking
if (bNewTable) {
// For any new table, the insertion location should be clean. We check for this here.
if (myRev32(ramEntryNext->header)!=0) {
MY_ERR("WARNING : Table entry location should be empty for a new table. Check code and image. Dumping data:\n");
MY_ERR("\theader = 0x%08x\n",myRev32(ramEntryNext->header));
MY_ERR("\tinstr = 0x%08x\n",myRev32(ramEntryNext->instr));
MY_ERR("\tdata = 0x%016llx\n",myRev64(ramEntryNext->data));
rc = IMGBUILD_WARN_RAM_TABLE_CONTAMINATION;
}
}
// ..insert the new Ram entry.
ramEntryNext->header = myRev32(ramEntryThis.header);
ramEntryNext->instr = myRev32(ramEntryThis.instr);
ramEntryNext->data = myRev64(ramEntryThis.data);
return rc;
}
/*
// io_image - Pointer to SLW image.
// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
// i_scomAddr - Scom address.
// i_coreId - The core ID [0:15].
// i_scomData - Data to write to scom register.
// i_operation - What to do with the scom addr and data.
// i_section - 0: General Scoms, 1: L2 cache, 2: L3 cache.
*/
uint32_t p8_pore_gen_scom_fixed(void *io_image,
uint8_t i_modeBuild,
uint32_t i_scomAddr,
uint32_t i_coreId, // [0:15]
uint64_t i_scomData,
uint32_t i_operation, // [0:7]
uint32_t i_section) // [0,1,2]
{
uint32_t rc=0, rcLoc=0, iEntry=0;
uint32_t chipletId=0;
uint32_t operation=0;
uint32_t entriesCount=0, entriesMatch=0, entriesNOP=0;
void *hostSlwSection;
void *hostSlwSectionFixed;
uint64_t xipScomTableThis;
void *hostScomVector, *hostScomTableThis;
void *hostScomEntryNext; // running entry pointer
void *hostScomEntryMatch=NULL; // pointer to entry that matches scomAddr
void *hostScomEntryRET=NULL; // pointer to first return instr after table
void *hostScomEntryNOP=NULL; // pointer to first nop IIS
uint8_t bufIIS[XIPSIZE_SCOM_ENTRY], bufNOP[4], bufRET[4];
SbeXipSection xipSection;
SbeXipItem xipTocItem;
PoreInlineContext ctx;
// -------------------------------------------------------------------------
// Validate Scom parameters.
//
// ...check if valid Scom register (is there anything we can do here to check?)
// Skipping check. We blindly trust caller.
//
// ...check mode build
if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE) {
MY_ERR("modeBuild=%i invalid. Valid range is [0;%i].",
i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE);
rcLoc = 1;
}
// ...check Scom operation
if (i_operation>P8_PORE_SCOM_LAST_OP) {
MY_ERR("Scom operation = %i is not within valid range of [%d;%d]\n",
i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP);
rcLoc = 1;
}
// ...check that core ID corresponds to valid chiplet ID
chipletId = i_coreId + P8_CID_EX_LOW;
if (chipletId<P8_CID_EX_LOW || chipletId>P8_CID_EX_HIGH) {
MY_ERR("Chiplet ID = 0x%02x is not within valid range of [0x%02x;0x%02x]\n",
chipletId, P8_CID_EX_LOW, P8_CID_EX_HIGH);
rcLoc = 1;
}
if (rcLoc)
return IMGBUILD_ERR_SCOM_INVALID_PARM;
rcLoc = 0;
// -------------------------------------------------------------------------
// Check slw section location and size. (Mainly needed for fixed image.)
//
if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image.
hostSlwSectionFixed = (void*)( (uintptr_t)io_image +
FIXED_SLW_IMAGE_SIZE -
FIXED_FFDC_SECTION_SIZE -
FIXED_SLW_SECTION_SIZE );
// Even though we shouldn't call this api during a rebuild, it should be
// safe to do so in this particular case since none of the info requested
// is supposed to be moved during a rebuild.
rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
if (rc) {
MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
return IMGBUILD_ERR_GET_SECTION;
}
hostSlwSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
if (hostSlwSectionFixed!=hostSlwSection) {
MY_ERR("hostSlwSectionFixed != hostSlwSection(from image api).\n");
return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD;
}
else {
MY_INF("hostSlwSectionFixed == hostSlwSection(from image api).\n");
}
}
else { // SRAM non-fixed image.
rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
if (rc) {
MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
return IMGBUILD_ERR_GET_SECTION;
}
hostSlwSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
}
// -------------------------------------------------------------------------
// Check .slw section size and cross-check w/header define.
//
if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE) {
MY_ERR("SLW table size in *.H header file (=%ld) differs from SLW section size in image (=%i).\n",FIXED_SLW_SECTION_SIZE,xipSection.iv_size);
MY_ERR("Check code or image version.\n");
return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD;
}
// -------------------------------------------------------------------------
// Summarize parameters and checking results.
//
MY_INF("Input parameter checks - OK\n");
MY_INF("\tRegister = 0x%08x\n",i_scomAddr);
MY_INF("\tOperation = %i\n",i_operation);
MY_INF("\tSection = %i\n",i_section);
MY_INF("\tCore ID = %i\n",i_coreId);
MY_INF("Image validation and size checks - OK\n");
MY_INF("\tSLW section size= %i\n",xipSection.iv_size);
// -------------------------------------------------------------------------
// Locate Scom vector according to i_section and then locate Scom table
// associated with "This" core ID.
//
if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image.
switch (i_section) {
case P8_SCOM_SECTION_NC:
hostScomTableThis = (void*)( (uintptr_t)hostSlwSection +
SLW_RAM_TABLE_SIZE +
SLW_SCOM_TABLE_SPACE_PER_CORE_NC*i_coreId );
break;
case P8_SCOM_SECTION_L2:
hostScomTableThis = (void*)( (uintptr_t)hostSlwSection +
SLW_RAM_TABLE_SIZE +
SLW_SCOM_TABLE_SIZE_NC +
SLW_SCOM_TABLE_SPACE_PER_CORE_L2*i_coreId );
break;
case P8_SCOM_SECTION_L3:
hostScomTableThis = (void*)( (uintptr_t)hostSlwSection +
SLW_RAM_TABLE_SIZE +
SLW_SCOM_TABLE_SIZE_NC +
SLW_SCOM_TABLE_SIZE_L2 +
SLW_SCOM_TABLE_SPACE_PER_CORE_L3*i_coreId );
break;
default:
MY_ERR("Invalid value for i_section (=%i).\n",i_section);
MY_ERR("Valid values for i_section = [%i,%i,%i].\n",
P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3);
return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION;
break;
}
}
else { // SRAM non-fixed image.
switch (i_section) {
case P8_SCOM_SECTION_NC:
rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem);
if (rc) {
MY_ERR("Probably invalid key word for SLW_HOST_SCOM_NC_VECTOR_TOC_NAME.\n");
return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
}
break;
case P8_SCOM_SECTION_L2:
rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L2_VECTOR_TOC_NAME, &xipTocItem);
if (rc) {
MY_ERR("Probably invalid key word for SLW_HOST_SCOM_L2_VECTOR_TOC_NAME.\n");
return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
}
break;
case P8_SCOM_SECTION_L3:
rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L3_VECTOR_TOC_NAME, &xipTocItem);
if (rc) {
MY_ERR("Probably invalid key word for SLW_HOST_SCOM_L3_VECTOR_TOC_NAME.\n");
return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
}
break;
default:
MY_ERR("Invalid value for i_section (=%i).\n",i_section);
MY_ERR("Valid values for i_section = [%i,%i,%i].\n",
P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3);
return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION;
}
MY_INF("xipTocItem.iv_address = 0x%016llx\n",xipTocItem.iv_address);
sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVector);
MY_INF("hostScomVector = 0x%016llx\n",(uint64_t)hostScomVector);
xipScomTableThis = myRev64(*((uint64_t*)hostScomVector + i_coreId));
MY_INF("xipScomTableThis = 0x%016llx\n",xipScomTableThis);
if (xipScomTableThis) {
sbe_xip_pore2host( io_image, xipScomTableThis, &hostScomTableThis);
}
else { // Should never be here.
MY_ERR("Code or image bug. Scom vector table entries should never be null.\n");
return IMGBUILD_ERR_CHECK_CODE;
}
}
//
// Determine where to place/do Scom action and if entry already exists.
// Insertion rules:
// - If entry doesn't exist, insert at first NOP. (Note that if you don't do
// this, then the table might potentially overflow since the max table size
// doesn't include NOP entries.)
// - If no NOP found, insert at first RET.
//
//----------------------------------------------------------------------------
// 1. Create search strings for addr, nop and ret.
//----------------------------------------------------------------------------
// Note, the following IIS will also be used in case of
// - i_operation==append
// - i_operation==replace
pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0);
pore_LS( &ctx, P1, chipletId);
pore_STI( &ctx, i_scomAddr, P1, i_scomData);
if (ctx.error > 0) {
MY_ERR("pore_LS or _STI generated rc = %d", ctx.error);
return IMGBUILD_ERR_PORE_INLINE_ASM;
}
pore_inline_context_create( &ctx, (void*)bufRET, 4, 0, 0);
pore_RET( &ctx);
if (ctx.error > 0) {
MY_ERR("pore_RET generated rc = %d", ctx.error);
return IMGBUILD_ERR_PORE_INLINE_ASM;
}
pore_inline_context_create( &ctx, (void*)bufNOP, 4, 0, 0);
pore_NOP( &ctx);
if (ctx.error > 0) {
MY_ERR("pore_NOP generated rc = %d", ctx.error);
return IMGBUILD_ERR_PORE_INLINE_ASM;
}
//----------------------------------------------------------------------------
// 2. Search for addr and nop in relevant coreId table until first RET.
//----------------------------------------------------------------------------
// Note:
// - We go through ALL entries until first RET instr. We MUST find a RET instr,
// though we don't check for overrun until later. (Could be improved.)
// - Count number of entries, incl the NOOPs, until we find an RET.
// - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry.
// - For an append operation, if a NOP is found (before a RET obviously), the
// SCOM is replacing that NNNN sequence.
hostScomEntryNext = hostScomTableThis;
MY_INF("hostScomEntryNext (addr): 0x%016llx\n ",(uint64_t)hostScomEntryNext);
while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t))) {
entriesCount++;
MY_INF("Number of SCOM entries: %i\n ",entriesCount);
if (*((uint32_t*)bufIIS+1)==*((uint32_t*)hostScomEntryNext+1) && entriesMatch==0) {// +1 skips 1st word in Scom entry (which loads the PC in an LS operation.)
hostScomEntryMatch = hostScomEntryNext;
entriesMatch++;
}
if (memcmp(hostScomEntryNext, bufNOP, sizeof(uint32_t))==0 && entriesNOP==0) {
hostScomEntryNOP = hostScomEntryNext;
entriesNOP++;
}
hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY);
}
hostScomEntryRET = hostScomEntryNext; // The last EntryNext is always the first RET.
//----------------------------------------------------------------------------
// 3. Qualify (translate) operation and IIS.
//----------------------------------------------------------------------------
if (i_operation==P8_PORE_SCOM_APPEND)
{
operation = i_operation;
}
else if (i_operation==P8_PORE_SCOM_REPLACE)
{
if (hostScomEntryMatch)
// ... do a replace
operation = i_operation;
else
// ... do an append
operation = P8_PORE_SCOM_APPEND;
}
else if (i_operation==P8_PORE_SCOM_NOOP)
{
// ...overwrite earlier bufIIS from the search step
pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0);
pore_NOP( &ctx);
pore_NOP( &ctx);
pore_NOP( &ctx);
pore_NOP( &ctx);
if (ctx.error > 0) {
MY_ERR("*** _NOP generated rc = %d", ctx.error);
return IMGBUILD_ERR_PORE_INLINE_ASM;
}
operation = i_operation;
}
else if ( i_operation==P8_PORE_SCOM_AND ||
i_operation==P8_PORE_SCOM_OR )
{
operation = i_operation;
}
else if ( i_operation==P8_PORE_SCOM_AND_APPEND )
{
if (hostScomEntryMatch)
// ... do the AND on existing Scom
operation = P8_PORE_SCOM_AND;
else
// ... do an append (this better be to an _AND register type)
operation = P8_PORE_SCOM_APPEND;
}
else if ( i_operation==P8_PORE_SCOM_OR_APPEND )
{
if (hostScomEntryMatch)
// ... do the OR on existing Scom
operation = P8_PORE_SCOM_OR;
else
// ... do an append (this better be to an _OR register type)
operation = P8_PORE_SCOM_APPEND;
}
else if (i_operation==P8_PORE_SCOM_RESET)
{
// ... create RNNN instruction sequence.
pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0);
pore_RET( &ctx);
pore_NOP( &ctx);
pore_NOP( &ctx);
pore_NOP( &ctx);
if (ctx.error > 0) {
MY_ERR("***_RET or _NOP generated rc = %d", ctx.error);
return IMGBUILD_ERR_PORE_INLINE_ASM;
}
operation = i_operation;
}
else
{
MY_ERR("Scom operation = %i is not within valid range of [%d;%d]\n",
i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP);
return IMGBUILD_ERR_SCOM_INVALID_PARM;
}
//----------------------------------------------------------------------------
// 4. Check for overrun.
//----------------------------------------------------------------------------
// Note:
// - An entry count exceeding the max allocated entry count will result in a code error
// because the allocation is based on an agreed upon max number of entries and
// therefore either the code header file needs to change or the caller is not abiding
// by the rules.
// - An entry count equalling the max allocated entry count is allowed for all commands
// except the APPEND command, incl the translated REPLACE->APPEND, which will result
// in the previously mentioned code error being returned.
// - The table can be full but still include NOOPs. If so, we can still APPEND since
// we append at first occurrence of a NOOP or at the end of the table (at the RET).
switch (i_section) {
case P8_SCOM_SECTION_NC:
if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_NC) &&
hostScomEntryNOP==NULL ) ||
entriesCount>SLW_MAX_SCOMS_NC )
{
MY_ERR("SCOM table NC is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_NC);
return IMGBUILD_ERR_CHECK_CODE;
}
break;
case P8_SCOM_SECTION_L2:
if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_L2) &&
hostScomEntryNOP==NULL ) ||
entriesCount>SLW_MAX_SCOMS_L2 )
{
MY_ERR("SCOM table L2 is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_L2);
return IMGBUILD_ERR_CHECK_CODE;
}
break;
case P8_SCOM_SECTION_L3:
if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_L3) &&
hostScomEntryNOP==NULL ) ||
entriesCount>SLW_MAX_SCOMS_L3 )
{
MY_ERR("SCOM table L3 is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_L3);
return IMGBUILD_ERR_CHECK_CODE;
}
break;
default:
MY_ERR("Invalid value for i_section (=%i).\n",i_section);
MY_ERR("Valid values for i_section = [%i,%i,%i].\n",
P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3);
return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION;
}
// ---------------------------------------------------------------------------
// 5. Insert the SCOM.
// ---------------------------------------------------------------------------
// Assuming pre-allocated Scom table (after pre-allocated Ram table):
// - Table is pre-filled with RNNN ISS.
// - Each core Id has dedicated space, uniformly distributed by SLW_MAX_SCOMS_NC*
// XIPSIZE_SCOM_ENTRY.
// - Remember to check for more than SLW_MAX_SCOMS_NC entries!
switch (operation) {
case P8_PORE_SCOM_APPEND: // Append a Scom at first occurring NNNN or RNNN,
if (hostScomEntryNOP) {
// ... replace the NNNN
MY_INF("Append at NOP\n");
memcpy(hostScomEntryNOP,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
}
else if (hostScomEntryRET) {
// ... replace the RNNN
MY_INF("Append at RET\n");
memcpy(hostScomEntryRET,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
}
else {
// We should never be here.
MY_ERR("In case=_SCOM_APPEND: EntryRET=NULL is impossible. Check code.\n");
return IMGBUILD_ERR_CHECK_CODE;
}
break;
case P8_PORE_SCOM_REPLACE: // Replace existing Scom with new data
if (hostScomEntryMatch) {
// ... do a vanilla replace
MY_INF("Replace existing Scom\n");
memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
}
else {
// We should never be here.
MY_ERR("In case=_SCOM_REPLACE: EntryMatch=NULL is impossible. Check code.\n");
return IMGBUILD_ERR_CHECK_CODE;
}
break;
case P8_PORE_SCOM_NOOP:
if (hostScomEntryMatch) {
// ... do a vanilla replace
MY_INF("Replace existing Scom w/NOPs\n");
memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
}
else {
MY_ERR("No Scom entry found to replace NOOPs with.\n");
return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
}
break;
case P8_PORE_SCOM_OR: // Overlay Scom data onto existing data by bitwise OR
if (hostScomEntryMatch) {
// ... do an OR on the data (which is the 2nd DWord in the entry)
MY_INF("Overlay existing Scom - OR case\n");
*((uint64_t*)hostScomEntryMatch+1) =
*((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData);
}
else {
MY_ERR("No Scom entry found to do OR operation with.\n");
return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
}
break;
case P8_PORE_SCOM_AND: // Overlay Scom data onto existing data by bitwise AND
if (hostScomEntryMatch) {
// ... do an AND on the data (which is the 2nd DWord in the entry)
MY_INF("Overlay existing Scom - AND case\n");
*((uint64_t*)hostScomEntryMatch+1) =
*((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData);
}
else {
MY_ERR("No Scom entry found to do AND operation with.\n");
return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
}
break;
case P8_PORE_SCOM_RESET: // Reset (delete) table. Refill w/RNNN ISS.
MY_INF("Reset table\n");
hostScomEntryNext = hostScomTableThis;
for ( iEntry=0; iEntry<entriesCount; iEntry++) {
memcpy( hostScomEntryNext, (void*)bufIIS, XIPSIZE_SCOM_ENTRY);
hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY);
}
break;
default:
MY_ERR("Impossible value of operation (=%i). Check code.\n",operation);
return IMGBUILD_ERR_CHECK_CODE;
} // End of switch(operation)
return rc;
}