BOOLEAN STATIC MemTHwWlPart2 ( IN OUT MEM_TECH_BLOCK *TechPtr ) { BOOLEAN retVal; retVal = TRUE; while (TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) { TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { if (!memTechTrainingFeatDDR3.HwBasedWLTrainingPart2 (TechPtr)) { retVal = FALSE; break; } MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); if (!memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { retVal = FALSE; break; } MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); } else { retVal = FALSE; break; } } return retVal; }
BOOLEAN STATIC MemNHwWlPart2Nb ( IN OUT MEM_TECH_BLOCK *TechPtr ) { BOOLEAN retVal; UINT8 i; retVal = TRUE; i = TechPtr->NBPtr->TrainingSequenceIndex; while ((TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) && (TechPtr->NBPtr->MemPstateStage != MEMORY_PSTATE_1ST_STAGE)) { TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) { retVal = FALSE; break; } MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { retVal = FALSE; break; } MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); } else { retVal = FALSE; break; } } return retVal; }
BOOLEAN MemNInitMCTNb ( IN OUT MEM_NB_BLOCK *NBPtr ) { MEM_TECH_BLOCK *TechPtr; UINT8 Dct; BOOLEAN Flag; ID_INFO CallOutIdInfo; TechPtr = NBPtr->TechPtr; // Switch Tech functions for Nb NBPtr->TechBlockSwitch (NBPtr); // Start Memory controller initialization sequence Flag = FALSE; if (TechPtr->DimmPresence (TechPtr)) { AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdCalcWidth (TechPtr)) { AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdGetTargetSpeed (TechPtr)) { for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { NBPtr->SwitchDCT (NBPtr, Dct); Flag |= MemNInitDCTNb (NBPtr); } if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { MemFInitTableDrive (NBPtr, MTBeforeDInit); AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); IDS_PERF_TIMESTAMP (TP_BEGINAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader)); CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId; CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId; IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId); AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr); IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 : (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 : (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); IDS_PERF_TIMESTAMP (TP_ENDAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader)); IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); NBPtr->StartupDCT (NBPtr); } } } } } return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); }
BOOLEAN MemNDQSTiming3Nb ( IN OUT MEM_NB_BLOCK *NBPtr ) { MEM_TECH_BLOCK *TechPtr; TechPtr = NBPtr->TechPtr; if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { // Right now we do not have anything to do if the callout is implemented } AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); //Execute Technology specific training features if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) { if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); // If target speed is higher than start-up speed, do frequency change and second pass of WL if (MemTHwWlPart2 (TechPtr)) { if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) { IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) { if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); do { if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); } } while (NBPtr->ChangeNbFrequency (NBPtr)); } } } } } } } } } } MemTMarkTrainFail (TechPtr); } return TRUE; }
BOOLEAN MemNInitMCTNb ( IN OUT MEM_NB_BLOCK *NBPtr ) { MEM_TECH_BLOCK *TechPtr; UINT8 Dct; BOOLEAN Flag; TechPtr = NBPtr->TechPtr; // Switch Tech functions for Nb NBPtr->TechBlockSwitch (NBPtr); // Start Memory controller initialization sequence Flag = FALSE; if (TechPtr->DimmPresence (TechPtr)) { AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdCalcWidth (TechPtr)) { AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdGetTargetSpeed (TechPtr)) { for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { NBPtr->SwitchDCT (NBPtr, Dct); Flag |= MemNInitDCTNb (NBPtr); } if (Flag && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { MemFInitTableDrive (NBPtr, MTBeforeDInit); AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); AgesaHookBeforeDramInit (0, NBPtr->MemPtr); AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); NBPtr->StartupDCT (NBPtr); } } } } } return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); }
/** * * * This function defines the memory initialization flow for * systems that only support DDR3 and KV processor. * * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK * * @return AGESA_STATUS * - AGESA_FATAL * - AGESA_CRITICAL * - AGESA_SUCCESS */ AGESA_STATUS MemMFlowD3KV ( IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr ) { MEM_NB_BLOCK *NBPtr; MEM_TECH_BLOCK *TechPtr; MEM_DATA_STRUCT *MemPtr; NBPtr = MemMainPtr->NBPtr; TechPtr = MemMainPtr->TechPtr; MemPtr = MemMainPtr->MemPtr; GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); if (!MemNIsIdSupportedKV (&(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { MemPtr->IsFlowControlSupported = FALSE; return AGESA_FATAL; } else { MemPtr->IsFlowControlSupported = TRUE; } MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeInitializeMCT); // Clear DisDllShutdownSR prior any P-State changes. MemNConfigureDisDllShutdownSrKV (NBPtr); //---------------------------------------------------------------- // Force NB-Pstate to NBP0 //---------------------------------------------------------------- MemNChangeNbFrequencyWrapUnb (NBPtr, 0); NBPtr->IsSupported[G5DimmInD3Socket] = FALSE; if (MemTDIMMPresence3 (NBPtr[BSP_DIE].TechPtr) && (NBPtr[BSP_DIE].MCTPtr->DimmPresent != 0)) { return MemMD3FlowKV (MemMainPtr); } else { PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); return AGESA_FATAL; // No DIMMs found } }
/** * * * This function defines the DDR3 initialization flow * when only DDR3 DIMMs are present in the system * * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK * * @return AGESA_STATUS * - AGESA_FATAL * - AGESA_CRITICAL * - AGESA_SUCCESS */ AGESA_STATUS MemMD3FlowKV ( IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr ) { UINT8 Dct; MEM_NB_BLOCK *NBPtr; MEM_DATA_STRUCT *MemPtr; ID_INFO CallOutIdInfo; INT8 MemPstate; UINT8 LowestMemPstate; UINT8 PmuImage; BOOLEAN ErrorRecovery; BOOLEAN IgnoreErr; NBPtr = &MemMainPtr->NBPtr[BSP_DIE]; MemPtr = MemMainPtr->MemPtr; ErrorRecovery = TRUE; IgnoreErr = FALSE; IDS_HDT_CONSOLE (MEM_FLOW, "DDR3 Mode\n"); //---------------------------------------------------------------- // Defines DDR3 registers //---------------------------------------------------------------- MemNInitNBRegTableD3KV (NBPtr); //---------------------------------------------------------------- // Clock and power gate unsued channels //---------------------------------------------------------------- MemNClockAndPowerGateUnusedDctKV (NBPtr); //---------------------------------------------------------------- // Set DDR3 mode //---------------------------------------------------------------- MemNSetDdrModeD3KV (NBPtr); //---------------------------------------------------------------- // Enable PHY Calibration //---------------------------------------------------------------- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctDimmValid != 0) { MemNEnablePhyCalibrationKV (NBPtr); } } //---------------------------------------------------------------- // Low voltage DDR3 //---------------------------------------------------------------- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); if (!MemFeatMain.LvDDR3 (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Find the maximum speed that all DCTs are capable running at //---------------------------------------------------------------- if (!MemTSPDGetTargetSpeed3 (NBPtr->TechPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Adjust memClkFreq based on MaxDdrRate //---------------------------------------------------------------- MemNAdjustDdrSpeed3Unb (NBPtr); //------------------------------------------------ // Finalize target frequency //------------------------------------------------ if (!MemMLvDdr3PerformanceEnhFinalize (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Program DCT address map //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "DCT addr map\n"); for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) { MemNDisableDctKV (NBPtr); } else { IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS Addr Map\n"); if (MemTSPDSetBanks3 (NBPtr->TechPtr)) { if (MemNStitchMemoryNb (NBPtr)) { if (NBPtr->DCTPtr->Timings.CsEnabled == 0) { MemNDisableDctKV (NBPtr); } else { IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAuto Cfg\n"); MemNAutoConfigKV (NBPtr); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTraining Cfg\n"); MemNConfigureDctForTrainingD3KV (NBPtr); } } } } } IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(MemMainPtr->MemPtr->StdHeader)); //---------------------------------------------------------------- // Init Phy mode //---------------------------------------------------------------- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); // 1. Program D18F2x9C_x0002_0099_dct[3:0][PmuReset,PmuStall] = 1,1. // 2. Program D18F2x9C_x0002_000E_dct[3:0][PhyDisable]=0. Tester_mode=0. MemNPmuResetNb (NBPtr); // 3. According to the type of DRAM attached, program D18F2x9C_x00FFF04A_dct[3:0][MajorMode], // D18F2x9C_x0002_000E_dct[3:0][G5_Mode], and D18F2x9C_x0002_0098_dct[3:0][CalG5D3]. // D18F2x9C_x0[3,1:0][F,7:0]1_[F,B:0]04A_dct[3:0]. MemNSetPhyDdrModeKV (NBPtr, DRAM_TYPE_DDR3_KV); // Work-around for CPU A0/A1, PhyReceiverPowerMode if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F15_KV_A0) != 0) { MemNPrePhyReceiverLowPowerKV (NBPtr); } } } //---------------------------------------------------------------- // Temporary buffer for DRAM CAD Bus Configuration //---------------------------------------------------------------- if (!MemNInitDramCadBusConfigKV (NBPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Program Mem Pstate dependent registers //---------------------------------------------------------------- IEM_SKIP_CODE (IEM_EARLY_DCT_CONFIG) { // PMU required M1 settings regardless Memory Pstate disabled. LowestMemPstate = 1; } for (MemPstate = LowestMemPstate; MemPstate >= 0; MemPstate--) { // When memory pstate is enabled, this loop will goes through M1 first then M0 // Otherwise, this loop only goes through M0. MemNSwitchMemPstateKV (NBPtr, MemPstate); // By default, start up speed is DDR667 for M1 // For M0, we need to set speed to highest possible frequency if (MemPstate == 0) { for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); NBPtr->DCTPtr->Timings.Speed = NBPtr->DCTPtr->Timings.TargetSpeed; } } IDS_HDT_CONSOLE (MEM_FLOW, "MemClkFreq = %d MHz\n", NBPtr->DCTPtr->Timings.Speed); // Program SPD timings and frequency dependent settings for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSPD timings\n"); if (MemTAutoCycTiming3 (NBPtr->TechPtr)) { IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMemPs Reg\n"); MemNProgramMemPstateRegD3KV (NBPtr, MemPstate); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tPlatform Spec\n"); if (MemNPlatformSpecKV (NBPtr)) { MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0); // 7. Program default CAD bus values. // 8. Program default data bus values. IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCAD Data Bus Cfg\n"); MemNProgramCadDataBusD3KV (NBPtr); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tPredriver\n"); MemNPredriverInitKV (NBPtr); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMode Register initialization\n"); MemNModeRegisterInitializationKV (NBPtr); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDRAM PHY Power Savings\n"); MemNDramPhyPowerSavingsKV (NBPtr); } } } } MemFInitTableDrive (NBPtr, MTBeforeDInit); } //---------------------------------------------------------------- // Program Phy //---------------------------------------------------------------- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); // 4. Program general phy static configuration. See 2.10.7.3.1. MemNPhyGenCfgKV (NBPtr); // 5. Phy Voltage Level Programming. See 2.10.7.3.2. MemNPhyVoltageLevelKV (NBPtr); // 6. Program DRAM channel frequency. See 2.10.7.3.3. MemNProgramChannelFreqKV (NBPtr, DRAM_TYPE_DDR3_KV); // Step 7 and 8 are done in MemPs dependent section // 9. Program FIFO pointer init values. See 2.10.7.3.6. MemNPhyFifoConfigD3KV (NBPtr); } } IEM_INSERT_CODE (IEM_EARLY_DEVICE_INIT, IemEarlyDeviceInitD3KV, (NBPtr)); //------------------------------------------------ // Callout before Dram Init //------------------------------------------------ AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(MemMainPtr->MemPtr->StdHeader)); CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId; CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId; //------------------------------------------------------------------------ // Callout to Platform BIOS to set the VDDP/VDDR voltage based upon Bit 21 // ProductIdentification Register (Dev18Fun3x1FC) //------------------------------------------------------------------------ if (MemNGetBitFieldNb (NBPtr, BFVddpVddrLowVoltSupp)) { MemMainPtr->MemPtr->ParameterListPtr->VddpVddrVoltage.Voltage = VOLT0_95; MemMainPtr->MemPtr->ParameterListPtr->VddpVddrVoltage.IsValid = TRUE; NBPtr->DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY; } else { MemMainPtr->MemPtr->ParameterListPtr->VddpVddrVoltage.IsValid = FALSE; } IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d, Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId); AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, MemMainPtr->MemPtr); NBPtr[BSP_DIE].FamilySpecificHook[AmpVoltageDisp] (&NBPtr[BSP_DIE], NULL); IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 : (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 : (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); //---------------------------------------------------------------------------- // Deassert MemResetL //---------------------------------------------------------------------------- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { // Deassert Procedure: // MemResetL = 0 // Go to LP2 // Go to PS0 MemNSetBitFieldNb (NBPtr, BFMemResetL, 0); MemNSetBitFieldNb (NBPtr, RegPwrStateCmd, 4); MemNSetBitFieldNb (NBPtr, RegPwrStateCmd, 0); } } MemUWait10ns (20000, NBPtr->MemPtr); //---------------------------------------------------------------------------- // Program PMU SRAM Message Block, Initiate PMU based Dram init and training //---------------------------------------------------------------------------- for (PmuImage = 0; PmuImage < MemNNumberOfPmuFirmwareImageKV (NBPtr); ++PmuImage) { NBPtr->PmuFirmwareImage = PmuImage; NBPtr->FeatPtr->LoadPmuFirmware (NBPtr); for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_STATUS, "Dct %d\n", Dct); IDS_HDT_CONSOLE (MEM_FLOW, "Initialize the PMU SRAM Message Block buffer\n"); if (MemNInitPmuSramMsgBlockKV (NBPtr) == FALSE) { IDS_HDT_CONSOLE (MEM_FLOW, "\tNot able to initialize the PMU SRAM Message Block buffer\n"); // Not able to initialize the PMU SRAM Message Block buffer. Log an event. PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_PMU_SRAM_MSG_BLOCK, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); return AGESA_FATAL; } for (MemPstate = LowestMemPstate; MemPstate >= 0; MemPstate--) { // When memory pstate is enabled, this loop will goes through M1 first then M0 // Otherwise, this loop only goes through M0. MemNSwitchMemPstateKV (NBPtr, MemPstate); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tPMU MemPs Reg\n"); MemNPopulatePmuSramTimingsD3KV (NBPtr); } MemNPopulatePmuSramConfigD3KV (NBPtr); MemNSetPmuSequenceControlKV (NBPtr); if (MemNWritePmuSramMsgBlockKV (NBPtr) == FALSE) { IDS_HDT_CONSOLE (MEM_FLOW, "\tNot able to load the PMU SRAM Message Block in to DMEM\n"); // Not able to load the PMU SRAM Message Block in to DMEM. Log an event. PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_LOCATE_FOR_PMU_SRAM_MSG_BLOCK, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); return AGESA_FATAL; } // Query for the calibrate completion. MemNPendOnPhyCalibrateCompletionKV (NBPtr); // Set calibration rate. MemNStartPmuNb (NBPtr); } } for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); if (MemNPendOnPmuCompletionNb (NBPtr) == FALSE) { PutEventLog (AGESA_FATAL, MEM_ERROR_PMU_TRAINING, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); AGESA_TESTPOINT (TpProcMemPmuFailed, &(MemMainPtr->MemPtr->StdHeader)); IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, &(MemMainPtr->MemPtr->StdHeader)); if (ErrorRecovery) { IDS_HDT_CONSOLE (MEM_FLOW, "Chipselects that PMU failed training %x\n",MemNGetBitFieldNb (NBPtr, PmuTestFail)); NBPtr->DCTPtr->Timings.CsTrainFail = (UINT16) MemNGetBitFieldNb (NBPtr, PmuTestFail); NBPtr->MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; } else { IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, &(MemMainPtr->MemPtr->StdHeader)); if (!(IgnoreErr)) { return AGESA_FATAL; } } } MemNRateOfPhyCalibrateKV (NBPtr); } } } //---------------------------------------------------------------- // De-allocate the PMU SRAM Message Block buffer. //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "De-allocate PMU SRAM Message Block buffer\n"); if (MemNPostPmuSramMsgBlockKV (NBPtr) == FALSE) { IDS_HDT_CONSOLE (MEM_FLOW, "\tNot able to free the PMU SRAM Message Block buffer\n"); // Not able to free the PMU SRAM Message Block buffer. Log an event. PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_DEALLOCATE_FOR_PMU_SRAM_MSG_BLOCK, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); return AGESA_FATAL; } //---------------------------------------------------------------- // De-allocate temporary buffer for DRAM CAD Bus Configuration //---------------------------------------------------------------- if (!MemNPostDramCadBusConfigKV (NBPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Disable chipselects that failed training //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDIMM Excludes\n"); MemNDimmExcludesKV (NBPtr); //---------------------------------------------------------------- // Synchronize Channels //---------------------------------------------------------------- MemNSyncChannelInitKV (NBPtr); //---------------------------------------------------------------- // Train MaxRdLatency //---------------------------------------------------------------- IEM_SKIP_CODE (IEM_LATE_DCT_CONFIG) { NBPtr->TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyTrainedByPmuByte; NBPtr->TechPtr->ResetDCTWrPtr = MemNResetRcvFifoKV; MemTTrainMaxLatency (NBPtr->TechPtr); // The fourth loop will restore the Northbridge P-State control register // to the original value. for (NBPtr->NbFreqChgState = 1; NBPtr->NbFreqChgState <= 4; NBPtr->NbFreqChgState++) { if (!MemNChangeNbFrequencyWrapUnb (NBPtr, NBPtr->NbFreqChgState) || (NBPtr->NbFreqChgState == 4)) { break; } MemTTrainMaxLatency (NBPtr->TechPtr); } } //---------------------------------------------------------------- // Set MajorMode //---------------------------------------------------------------- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); // Work-around for CPU A0/A1, PhyReceiverPowerMode if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F15_KV_A0) != 0) { MemNPostPhyReceiverLowPowerKV (NBPtr); } } //---------------------------------------------------------------- // Configure DCT for normal operation //---------------------------------------------------------------- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMission mode cfg\n"); MemNConfigureDctNormalD3KV (NBPtr); //---------------------------------------------------------------- // Program turnaround timings //---------------------------------------------------------------- for (MemPstate = LowestMemPstate; MemPstate >= 0; MemPstate--) { MemNSwitchMemPstateKV (NBPtr, MemPstate); MemNProgramTurnaroundTimingsD3KV (NBPtr); //---------------------------------------------------------------- // After Mem Pstate1 Partial Training Table values //---------------------------------------------------------------- MemFInitTableDrive (NBPtr, MTAfterMemPstate1PartialTrn); } } } IEM_INSERT_CODE (IEM_LATE_DCT_CONFIG, IemLateDctConfigD3KV, (NBPtr)); for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdditional DRAM PHY Power Savings\n"); MemNAddlDramPhyPowerSavingsKV (NBPtr); } } //---------------------------------------------------------------- // Initialize Channels interleave address bit. //---------------------------------------------------------------- MemNInitChannelIntlvAddressBitKV (NBPtr); //---------------------------------------------------------------- // Assign physical address ranges for DCTs and node. Also, enable channel interleaving. //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tHT mem map\n"); if (!NBPtr->FeatPtr->InterleaveChannels (NBPtr)) { MemNHtMemMapKV (NBPtr); } //---------------------------------------------------- // If there is no dimm on the system, do fatal exit //---------------------------------------------------- if (NBPtr->RefPtr->SysLimit == 0) { PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); return AGESA_FATAL; } //---------------------------------------------------------------- // CpuMemTyping //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMem typing\n"); MemNCPUMemTypingNb (NBPtr); IDS_OPTION_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)); //---------------------------------------------------------------- // After Training Table values //---------------------------------------------------------------- MemFInitTableDrive (NBPtr, MTAfterTrn); //---------------------------------------------------------------- // Interleave banks //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tBank Intlv\n"); if (NBPtr->FeatPtr->InterleaveBanks (NBPtr)) { if (NBPtr->MCTPtr->ErrCode == AGESA_FATAL) { return AGESA_FATAL; } } //---------------------------------------------------------------- // After Programming Interleave registers //---------------------------------------------------------------- MemFInitTableDrive (NBPtr, MTAfterInterleave); //---------------------------------------------------------------- // Memory Clear //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); if (!MemFeatMain.MemClr (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // ECC //---------------------------------------------------------------- if (!MemFeatMain.InitEcc (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // C6 and ACP Engine Storage Allocation //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tC6 and ACP Engine Storage\n"); MemNAllocateC6AndAcpEngineStorageKV (NBPtr); //---------------------------------------------------------------- // UMA Allocation & UMAMemTyping //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tUMA Alloc\n"); if (!MemFeatMain.UmaAllocation (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // OnDimm Thermal //---------------------------------------------------------------- if (NBPtr->FeatPtr->OnDimmThermal (NBPtr)) { if (NBPtr->MCTPtr->ErrCode == AGESA_FATAL) { return AGESA_FATAL; } } //---------------------------------------------------------------- // Finalize MCT //---------------------------------------------------------------- MemNFinalizeMctKV (NBPtr); MemFInitTableDrive (NBPtr, MTAfterFinalizeMCT); //---------------------------------------------------------------- // Memory Context Save //---------------------------------------------------------------- MemFeatMain.MemSave (MemMainPtr); //---------------------------------------------------------------- // Memory DMI support //---------------------------------------------------------------- if (!MemFeatMain.MemDmi (MemMainPtr)) { return AGESA_CRITICAL; } //---------------------------------------------------------------- // Memory CRAT support //---------------------------------------------------------------- if (!MemFeatMain.MemCrat (MemMainPtr)) { return AGESA_CRITICAL; } //---------------------------------------------------------------- // Save memory S3 data //---------------------------------------------------------------- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tS3 Save\n"); if (!MemMS3Save (MemMainPtr)) { return AGESA_CRITICAL; } //---------------------------------------------------------------- // Switch back to DCT 0 before sending control back //---------------------------------------------------------------- MemNSwitchDCTNb (NBPtr, 0); return AGESA_SUCCESS; }
/** * * * This function defines the memory initialization flow for * systems that only support RB processors. * * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK * * @return AGESA_STATUS * - AGESA_ALERT * - AGESA_FATAL * - AGESA_SUCCESS * - AGESA_WARNING */ AGESA_STATUS MemMFlowDA ( IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr ) { UINT8 Node; UINT8 NodeCnt; MEM_NB_BLOCK *NBPtr; MEM_TECH_BLOCK *TechPtr; NBPtr = MemMainPtr->NBPtr; TechPtr = MemMainPtr->TechPtr; NodeCnt = MemMainPtr->DieCount; //---------------------------------------------------------------- // Initialize MCT //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); for (Node = 0; Node < NodeCnt; Node++) { if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { return AGESA_FATAL; } } //---------------------------------------------------------------- // Low voltage DDR3 //---------------------------------------------------------------- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); if (!MemFeatMain.LvDDR3 (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Initialize DRAM and DCTs, and Create Memory Map //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); for (Node = 0; Node < NodeCnt; Node++) { // Initialize Memory Controller and Dram IDS_HDT_CONSOLE ("!Node %d\n", Node); if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { return AGESA_FATAL; // fatalexit } // Create memory map AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { return AGESA_FATAL; } } //---------------------------------------------------- // If there is no dimm on the system, do fatal exit //---------------------------------------------------- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); ASSERT (FALSE); return AGESA_FATAL; } //---------------------------------------------------------------- // Synchronize DCTs //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); for (Node = 0; Node < NodeCnt; Node++) { if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { return AGESA_FATAL; } } //---------------------------------------------------------------- // CpuMemTyping //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { return AGESA_FATAL; } //---------------------------------------------------------------- // Before Training Table values //---------------------------------------------------------------- for (Node = 0; Node < NodeCnt; Node++) { MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); } //---------------------------------------------------------------- // Memory Context Restore //---------------------------------------------------------------- if (!MemFeatMain.MemRestore (MemMainPtr)) { // Do DQS training only if memory context restore fails //---------------------------------------------------------------- // Training //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); IDS_OPTION_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)); MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; if (!MemFeatMain.Training (MemMainPtr)) { return AGESA_FATAL; } IDS_HDT_CONSOLE ("\nEnd DQS training\n\n"); } //---------------------------------------------------------------- // Disable chipselects that fail training //---------------------------------------------------------------- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; MemFeatMain.ExcludeDIMM (MemMainPtr); MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; //---------------------------------------------------------------- // OtherTiming //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); for (Node = 0; Node < NodeCnt; Node++) { if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { return AGESA_FATAL; } } //---------------------------------------------------------------- // After Training Table values //---------------------------------------------------------------- for (Node = 0; Node < NodeCnt; Node++) { MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); } //---------------------------------------------------------------- // SetDqsEccTimings //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); for (Node = 0; Node < NodeCnt; Node++) { if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { return AGESA_FATAL; } } //---------------------------------------------------------------- // Online Spare //---------------------------------------------------------------- if (!MemFeatMain.OnlineSpare (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Interleave banks //---------------------------------------------------------------- for (Node = 0; Node < NodeCnt; Node++) { if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { return AGESA_FATAL; } } } //---------------------------------------------------------------- // Interleave Nodes //---------------------------------------------------------------- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Interleave channels //---------------------------------------------------------------- for (Node = 0; Node < NodeCnt; Node++) { if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { return AGESA_FATAL; } } } //---------------------------------------------------------------- // UMA Allocation & UMAMemTyping //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); if (!MemFeatMain.UmaAllocation (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Interleave region //---------------------------------------------------------------- NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); //---------------------------------------------------------------- // ECC //---------------------------------------------------------------- if (!MemFeatMain.InitEcc (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // Memory Clear //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); if (!MemFeatMain.MemClr (MemMainPtr)) { return AGESA_FATAL; } //---------------------------------------------------------------- // OnDimm Thermal //---------------------------------------------------------------- for (Node = 0; Node < NodeCnt; Node++) { if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { return AGESA_FATAL; } } } //---------------------------------------------------------------- // Finalize MCT //---------------------------------------------------------------- for (Node = 0; Node < NodeCnt; Node++) { if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { return AGESA_FATAL; } } //---------------------------------------------------------------- // Memory Context Save //---------------------------------------------------------------- MemFeatMain.MemSave (MemMainPtr); //---------------------------------------------------------------- // Memory DMI support //---------------------------------------------------------------- if (!MemFeatMain.MemDmi (MemMainPtr)) { return AGESA_CRITICAL; } return AGESA_SUCCESS; }
BOOLEAN memNSequenceDDR3Nb ( IN OUT MEM_NB_BLOCK *NBPtr ) { MEM_TECH_BLOCK *TechPtr; UINT8 i; TechPtr = NBPtr->TechPtr; i = NBPtr->TrainingSequenceIndex; if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) { AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n"); if (AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { // Right now we do not have anything to do if the callout is implemented } AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); //Execute Technology specific training features if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) { TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); // If target speed is higher than start-up speed, do frequency change and second pass of WL do { if (MemNHwWlPart2Nb (TechPtr)) { if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) { IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) { if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); if (!NBPtr->FamilySpecificHook[MemPstateStageChange] (NBPtr, NULL)) { continue; } if (NBPtr->Execute1dMaxRdLatTraining) { do { if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) { MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); } } while (NBPtr->ChangeNbFrequency (NBPtr)); } else { // If not running MRL training, set everything back for training memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr); } } } } } } } } while (NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE); } } } } MemTMarkTrainFail (TechPtr); } return TRUE; }
/** * * MemM2DTrainingWithAggressor * * This function implements standard memory training whereby training functions * for all nodes are run by the BSP while enabling other dies to eable argressor channel * * * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK * * @return TRUE - No fatal error occurs. * @return FALSE - Fatal error occurs. */ BOOLEAN MemM2DTrainingWithAggressor ( IN OUT MEM_MAIN_DATA_BLOCK *mmPtr ) { UINT8 Die; UINT8 Index; // // If training is disabled, return success. // if (!UserOptions.CfgDqsTrainingControl) { return TRUE; } mmPtr->mmSharedPtr->CommonSmallestMaxNegVref = 0x7F; mmPtr->mmSharedPtr->CommonSmallestMaxPosVref = 0x7F; // // Run Northbridge-specific Standard Training feature for each die. // IDS_HDT_CONSOLE (MEM_STATUS, "\nStart standard serial training\n"); for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = FALSE; mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { break; } } //---------------------------------------------------------------- // Determine Aggressor Chipselects for all DCTs on all nodes. //---------------------------------------------------------------- MemFeatMain.AggressorDetermination (mmPtr); IDS_HDT_CONSOLE (MEM_STATUS, "\nStart 2D training with agressors run independently\n"); for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) { //Execute Technology specific 2D training features Index = 0; while (memTrainSequenceDDR3[Index].TrainingSequenceEnabled != 0) { if (memTrainSequenceDDR3[Index].TrainingSequenceEnabled (&mmPtr->NBPtr[Die])) { mmPtr->NBPtr[Die].TrainingSequenceIndex = Index; // Execute 2D RdDqs Training memTrainSequenceDDR3[Index].MemTechFeatBlock->RdDqs2DTraining (mmPtr->NBPtr[Die].TechPtr); // Execute MaxRdLat Training After 2D training do { if (memTrainSequenceDDR3[Index].MemTechFeatBlock->MaxRdLatencyTraining (mmPtr->NBPtr[Die].TechPtr)) { MemFInitTableDrive (&mmPtr->NBPtr[Die], MTAfterMaxRdLatTrn); } } while (mmPtr->NBPtr->ChangeNbFrequency (&mmPtr->NBPtr[Die])); break; } Index++; } } mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL); mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { break; } } // End Die For Loop return (BOOLEAN) (Die == mmPtr->DieCount); }
/** * * MemMStandardTrainingUsingAdjacentDies * * This function implements standard memory training whereby training functions * for all nodes are run by the BSP while enabling other dies to eable argressor channel * * * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK * * @return TRUE - No fatal error occurs. * @return FALSE - Fatal error occurs. */ BOOLEAN MemMStandardTrainingUsingAdjacentDies ( IN OUT MEM_MAIN_DATA_BLOCK *mmPtr ) { UINT8 Die; UINT8 AdjacentDie; UINT32 AdjacentSocketNum; UINT32 TargetSocketNum; UINT32 ModuleNum; UINT8 i; UINT8 Dct; UINT8 ChipSel; BOOLEAN FirstCsFound; // // If training is disabled, return success. // if (!UserOptions.CfgDqsTrainingControl) { return TRUE; } mmPtr->mmSharedPtr->CommonSmallestMaxNegVref = 0x7F; mmPtr->mmSharedPtr->CommonSmallestMaxPosVref = 0x7F; // // Run Northbridge-specific Standard Training feature for each die. // IDS_HDT_CONSOLE (MEM_STATUS, "\nStart standard serial training\n"); for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = FALSE; mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { break; } } IDS_HDT_CONSOLE (MEM_STATUS, "\nStart 2D training with agressors\n"); for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); GetSocketModuleOfNode (Die, &TargetSocketNum, &ModuleNum, &(mmPtr->MemPtr->StdHeader)); for (AdjacentDie = 0; AdjacentDie < mmPtr->DieCount; AdjacentDie++) { mmPtr->NBPtr[Die].DieEnabled[AdjacentDie] = FALSE; GetSocketModuleOfNode (AdjacentDie, &AdjacentSocketNum, &ModuleNum, &(mmPtr->MemPtr->StdHeader)); if (TargetSocketNum == AdjacentSocketNum) { if (AdjacentDie != Die) { if (mmPtr->NBPtr[AdjacentDie].MCTPtr->NodeMemSize != 0) { mmPtr->NBPtr[Die].AdjacentDieNBPtr = &mmPtr->NBPtr[AdjacentDie]; mmPtr->NBPtr[Die].DieEnabled[AdjacentDie] = TRUE; } } else { if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) { mmPtr->NBPtr[Die].DieEnabled[Die] = TRUE; } } // Determine the initial target CS, Max Dimms and max CS number for all DCTs (potential aggressors) if (mmPtr->NBPtr[AdjacentDie].MCTPtr->NodeMemSize != 0) { for (Dct = 0; Dct < mmPtr->NBPtr[AdjacentDie].DctCount; Dct++) { FirstCsFound = FALSE; mmPtr->NBPtr[AdjacentDie].SwitchDCT (&mmPtr->NBPtr[AdjacentDie], Dct); for (ChipSel = 0; ChipSel < mmPtr->NBPtr[AdjacentDie].CsPerChannel; ChipSel = ChipSel + (mmPtr->NBPtr[Die].IsSupported[PerDimmAggressors2D] ? 2 : mmPtr->NBPtr[AdjacentDie].CsPerDelay) ) { if ((mmPtr->NBPtr[AdjacentDie].DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) { if (FirstCsFound == FALSE) { // Set Initial CS value for Current Aggressor CS mmPtr->NBPtr[AdjacentDie].InitialAggressorCSTarget[Dct] = ChipSel; mmPtr->NBPtr[AdjacentDie].CurrentAggressorCSTarget[Dct] = mmPtr->NBPtr[AdjacentDie].InitialAggressorCSTarget[Dct]; FirstCsFound = TRUE; } mmPtr->NBPtr[AdjacentDie].MaxAggressorCSEnabled[Dct] = ChipSel; mmPtr->NBPtr[AdjacentDie].MaxAggressorDimms[Dct]++; } } } } } } if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) { //Execute Technology specific 2D training features i = 0; while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) { if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (&mmPtr->NBPtr[Die])) { mmPtr->NBPtr[Die].TrainingSequenceIndex = i; // Execute 2D RdDqs Training memTrainSequenceDDR3[i].MemTechFeatBlock->RdDqs2DTraining (mmPtr->NBPtr[Die].TechPtr); // Execute MaxRdLat Training After 2D training do { if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (mmPtr->NBPtr[Die].TechPtr)) { MemFInitTableDrive (&mmPtr->NBPtr[Die], MTAfterMaxRdLatTrn); } } while (mmPtr->NBPtr->ChangeNbFrequency (&mmPtr->NBPtr[Die])); break; } i++; } } mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL); mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { break; } } return (BOOLEAN) (Die == mmPtr->DieCount); }