/**Function************************************************************* Synopsis [Derives the functionality of the supergate.] Description [This procedure is useful for verification the supergate library. The truth table derived by this procedure should be the same as the one contained in the original supergate file.] SideEffects [] SeeAlso [] ***********************************************************************/ void Map_LibraryComputeTruth_rec( Map_SuperLib_t * pLib, char * pFormula, unsigned uTruthsIn[][2], unsigned uTruthRes[] ) { Mio_Gate_t * pMioGate; char * pGateName, * pStrings[6]; unsigned uTruthsFanins[6][2]; int nStrings, i; // perform one step parsing of the formula // detect the root gate name, the next-step strings, and their number pGateName = Map_LibraryReadFormulaStep( pFormula, pStrings, &nStrings ); if ( nStrings == 0 ) // elementary variable { assert( pGateName[0] - 'a' < pLib->nVarsMax ); uTruthRes[0] = uTruthsIn[pGateName[0] - 'a'][0]; uTruthRes[1] = uTruthsIn[pGateName[0] - 'a'][1]; return; } // derive the functionality of the fanins for ( i = 0; i < nStrings; i++ ) Map_LibraryComputeTruth_rec( pLib, pStrings[i], uTruthsIn, uTruthsFanins[i] ); // get the root supergate pMioGate = Mio_LibraryReadGateByName( pLib->pGenlib, pGateName, NULL ); if ( pMioGate == NULL ) printf( "A supergate contains gate \"%s\" that is not in \"%s\".\n", pGateName, Mio_LibraryReadName(pLib->pGenlib) ); // derive the functionality of the output of the supergate Mio_DeriveTruthTable( pMioGate, uTruthsFanins, nStrings, pLib->nVarsMax, uTruthRes ); }
/**Function************************************************************* Synopsis [Creates the mapped network.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Abc_Obj_t * Abc_NodeFromMapSuper_rec( Abc_Ntk_t * pNtkNew, Map_Node_t * pNodeMap, Map_Super_t * pSuper, Abc_Obj_t * pNodePis[], int nNodePis ) { Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen(); Mio_Gate_t * pRoot; Map_Super_t ** ppFanins; Abc_Obj_t * pNodeNew, * pNodeFanin; int nFanins, Number, i; // get the parameters of the supergate pRoot = Map_SuperReadRoot(pSuper); if ( pRoot == NULL ) { Number = Map_SuperReadNum(pSuper); if ( Number < nNodePis ) { return pNodePis[Number]; } else { // assert( 0 ); /* It might happen that a super gate with 5 inputs is constructed that * actually depends only on the first four variables; i.e the fifth is a * don't care -- in that case we connect constant node for the fifth * (since the cut only has 4 variables). An interesting question is what * if the first variable (and not the fifth one is the redundant one; * can that happen?) */ return Abc_NtkCreateNodeConst0(pNtkNew); } } pRoot = Mio_LibraryReadGateByName( pLib, Mio_GateReadName(pRoot), NULL ); // get information about the fanins of the supergate nFanins = Map_SuperReadFaninNum( pSuper ); ppFanins = Map_SuperReadFanins( pSuper ); // create a new node with these fanins pNodeNew = Abc_NtkCreateNode( pNtkNew ); for ( i = 0; i < nFanins; i++ ) { pNodeFanin = Abc_NodeFromMapSuper_rec( pNtkNew, pNodeMap, ppFanins[i], pNodePis, nNodePis ); Abc_ObjAddFanin( pNodeNew, pNodeFanin ); } pNodeNew->pData = pRoot; return pNodeNew; }
/**Function************************************************************* Synopsis [This procedure transforms tech-ind Ptr into mapped Ptr.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Cba_PtrUpdateBox( Vec_Ptr_t * vBox, Vec_Ptr_t * vGatesNames ) { Mio_Gate_t * pGate; Mio_Pin_t * pPin; int i = 1; Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen( Abc_FrameGetGlobalFrame() ); // update gate name char * pNameNew, * pName = (char *)Vec_PtrEntry(vBox, 0); if ( !strcmp(pName, "Const0T") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_C0); else if ( !strcmp(pName, "Const1T") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_C1); else if ( !strcmp(pName, "BufT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_BUF); else if ( !strcmp(pName, "InvT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_INV); else if ( !strcmp(pName, "AndT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_AND); else if ( !strcmp(pName, "NandT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_NAND); else if ( !strcmp(pName, "OrT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_OR); else if ( !strcmp(pName, "NorT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_NOR); else if ( !strcmp(pName, "XorT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_XOR); else if ( !strcmp(pName, "XnorT") ) pNameNew = (char *)Vec_PtrEntry(vGatesNames, PTR_GATE_XNOR); else // user hierarchy return; ABC_FREE( pName ); Vec_PtrWriteEntry( vBox, 0, Abc_UtilStrsav(pNameNew) ); // remove instance name pName = (char *)Vec_PtrEntry(vBox, 1); ABC_FREE( pName ); Vec_PtrWriteEntry( vBox, 1, NULL ); // update formal input names pGate = Mio_LibraryReadGateByName( pLib, pNameNew, NULL ); Mio_GateForEachPin( pGate, pPin ) { pName = (char *)Vec_PtrEntry( vBox, 2 * i ); ABC_FREE( pName ); pNameNew = Mio_PinReadName(pPin); Vec_PtrWriteEntry( vBox, 2 * i++, Abc_UtilStrsav(pNameNew) ); }
ABC_NAMESPACE_IMPL_START //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// //////////////////////////////////////////////////////////////////////// /**Function************************************************************* Synopsis [] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ int Psr_ManIsMapped( Psr_Ntk_t * pNtk ) { Vec_Int_t * vSigs; int iBox; Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen(); if ( pLib == NULL ) return 0; Psr_NtkForEachBox( pNtk, vSigs, iBox ) if ( !Psr_BoxIsNode(pNtk, iBox) ) { int NtkId = Psr_BoxNtk( pNtk, iBox ); if ( Mio_LibraryReadGateByName(pLib, Psr_NtkStr(pNtk, NtkId), NULL) ) return 1; } return 0; }
/**Function************************************************************* Synopsis [] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ int Io_ReadBlifNetworkGate( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) { Mio_Library_t * pGenlib; Mio_Gate_t * pGate; Abc_Obj_t * pNode; char ** ppNames; int i, nNames; // check that the library is available pGenlib = (Mio_Library_t *)Abc_FrameReadLibGen(); if ( pGenlib == NULL ) { p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); sprintf( p->sError, "The current library is not available." ); Io_ReadBlifPrintErrorMessage( p ); return 1; } // create a new node and add it to the network if ( vTokens->nSize < 2 ) { p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); sprintf( p->sError, "The .gate line has less than two tokens." ); Io_ReadBlifPrintErrorMessage( p ); return 1; } // get the gate pGate = Mio_LibraryReadGateByName( pGenlib, (char *)vTokens->pArray[1] ); if ( pGate == NULL ) { p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); sprintf( p->sError, "Cannot find gate \"%s\" in the library.", (char*)vTokens->pArray[1] ); Io_ReadBlifPrintErrorMessage( p ); return 1; } // if this is the first line with gate, update the network type if ( Abc_NtkNodeNum(p->pNtkCur) == 0 ) { assert( p->pNtkCur->ntkFunc == ABC_FUNC_SOP ); p->pNtkCur->ntkFunc = ABC_FUNC_MAP; Mem_FlexStop( (Mem_Flex_t *)p->pNtkCur->pManFunc, 0 ); p->pNtkCur->pManFunc = pGenlib; } // reorder the formal inputs to be in the same order as in the gate if ( !Io_ReadBlifReorderFormalNames( vTokens, pGate ) ) { p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); sprintf( p->sError, "Mismatch in the fanins of gate \"%s\".", (char*)vTokens->pArray[1] ); Io_ReadBlifPrintErrorMessage( p ); return 1; } // remove the formal parameter names for ( i = 2; i < vTokens->nSize; i++ ) { vTokens->pArray[i] = Io_ReadBlifCleanName( (char *)vTokens->pArray[i] ); if ( vTokens->pArray[i] == NULL ) { p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); sprintf( p->sError, "Invalid gate input assignment." ); Io_ReadBlifPrintErrorMessage( p ); return 1; } } // create the node ppNames = (char **)vTokens->pArray + 2; nNames = vTokens->nSize - 3; pNode = Io_ReadCreateNode( p->pNtkCur, ppNames[nNames], ppNames, nNames ); // set the pointer to the functionality of the node Abc_ObjSetData( pNode, pGate ); return 0; }