void up_irqinitialize(void) { uint32_t regaddr; #ifdef CONFIG_DEBUG_FEATURES uint32_t regval; #endif int num_priority_registers; int i; /* Disable all interrupts */ for (i = 0; i < LPC43M4_IRQ_NEXTINT; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. */ putreg32((uint32_t)_vectors, NVIC_VECTAB); #ifdef CONFIG_ARCH_RAMVECTORS /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. */ up_ramvec_initialize(); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt * lines that the NVIC supports: * * 0 -> 32 interrupt lines, 8 priority registers * 1 -> 64 " " " ", 16 priority registers * 2 -> 96 " " " ", 32 priority registers * ... */ num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; /* Now set all of the interrupt lines to the default priority */ regaddr = NVIC_IRQ0_3_PRIORITY; while (num_priority_registers--) { putreg32(DEFPRIORITY32, regaddr); regaddr += 4; } /* currents_regs is non-NULL only while processing an interrupt */ CURRENT_REGS = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(LPC43_IRQ_SVCALL, up_svcall, NULL); irq_attach(LPC43_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI lpc43_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU irq_attach(LPC43_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(LPC43_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES irq_attach(LPC43_IRQ_NMI, lpc43_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(LPC43_IRQ_MEMFAULT, up_memfault, NULL); #endif irq_attach(LPC43_IRQ_BUSFAULT, lpc43_busfault, NULL); irq_attach(LPC43_IRQ_USAGEFAULT, lpc43_usagefault, NULL); irq_attach(LPC43_IRQ_PENDSV, lpc43_pendsv, NULL); irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_dbgmonitor, NULL); irq_attach(LPC43_IRQ_RESERVED, lpc43_reserved, NULL); #endif lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS); /* If a debugger is connected, try to prevent it from catching hardfaults. * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal * operation. */ #if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI) regval = getreg32(NVIC_DEMCR); regval &= ~NVIC_DEMCR_VCHARDERR; putreg32(regval, NVIC_DEMCR); #endif /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS up_irq_enable(); #endif }
void up_irqinitialize(void) { uint32_t regaddr; int num_priority_registers; int i; /* Disable all interrupts */ for (i = 0; i < NR_VECTORS - EFM32_IRQ_INTERRUPTS; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 /* Colorize the interrupt stack for debug purposes */ { size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size), intstack_size); } #endif /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. */ putreg32((uint32_t)_vectors, NVIC_VECTAB); #ifdef CONFIG_ARCH_RAMVECTORS /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. */ up_ramvec_initialize(); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt * lines that the NVIC supports: * * 0 -> 32 interrupt lines, 8 priority registers * 1 -> 64 " " " ", 16 priority registers * 2 -> 96 " " " ", 32 priority registers * ... */ num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; /* Now set all of the interrupt lines to the default priority */ regaddr = NVIC_IRQ0_3_PRIORITY; while (num_priority_registers--) { putreg32(DEFPRIORITY32, regaddr); regaddr += 4; } /* currents_regs is non-NULL only while processing an interrupt */ CURRENT_REGS = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(EFM32_IRQ_SVCALL, up_svcall); irq_attach(EFM32_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARMV7M_USEBASEPRI efm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU irq_attach(EFM32_IRQ_MEMFAULT, up_memfault); up_enable_irq(EFM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES irq_attach(EFM32_IRQ_NMI, efm32_nmi); #ifndef CONFIG_ARM_MPU irq_attach(EFM32_IRQ_MEMFAULT, up_memfault); #endif irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault); irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault); irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv); irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor); irq_attach(EFM32_IRQ_RESERVED, efm32_reserved); #endif efm32_dumpnvic("initial", NR_VECTORS); #ifndef CONFIG_SUPPRESS_INTERRUPTS #ifdef CONFIG_EFM32_GPIO_IRQ /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ efm32_gpioirqinitialize(); #endif /* And finally, enable interrupts */ up_irq_enable(); #endif }