void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor, u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu) { u32 d_cur; u32 p_emp; d_cur = tegra_sor_readl(sor, NV_SOR_DC(sor->portnum)); p_emp = tegra_sor_readl(sor, NV_SOR_PR(sor->portnum)); switch (lane) { case 0: p_emp &= ~NV_SOR_PR_LANE2_DP_LANE0_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE2_DP_LANE0_SHIFT); d_cur &= ~NV_SOR_DC_LANE2_DP_LANE0_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE2_DP_LANE0_SHIFT); break; case 1: p_emp &= ~NV_SOR_PR_LANE1_DP_LANE1_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE1_DP_LANE1_SHIFT); d_cur &= ~NV_SOR_DC_LANE1_DP_LANE1_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE1_DP_LANE1_SHIFT); break; case 2: p_emp &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE0_DP_LANE2_SHIFT); d_cur &= ~NV_SOR_DC_LANE0_DP_LANE2_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE0_DP_LANE2_SHIFT); break; case 3: p_emp &= ~NV_SOR_PR_LANE3_DP_LANE3_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE3_DP_LANE3_SHIFT); d_cur &= ~NV_SOR_DC_LANE3_DP_LANE3_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE3_DP_LANE3_SHIFT); break; default: printk(BIOS_SPEW, "dp: sor lane count %d is invalid\n", lane); } tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum), NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, tx_pu << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT); tegra_sor_writel(sor, NV_SOR_DC(sor->portnum), d_cur); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), p_emp); }
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg) { tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), link_cfg->drive_current); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), link_cfg->preemphasis); tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum), link_cfg->postcursor); tegra_sor_writel(sor, NV_SOR_LVDS, 0); tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), NV_SOR_DP_PADCTL_TX_PU_ENABLE | NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, NV_SOR_DP_PADCTL_TX_PU_ENABLE | 2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT); /* Precharge */ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), 0xf0, 0xf0); udelay(20); tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), 0xf0, 0x0); }
void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported) { tegra_sor_write_field(sor, NV_SOR_PR(sor->portnum), mask, pe_reg); tegra_sor_write_field(sor, NV_SOR_DC(sor->portnum), mask, vs_reg); if (pc_supported) { tegra_sor_write_field( sor, NV_SOR_POSTCURSOR(sor->portnum), mask, pc_reg); } }
void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor) { u32 drive_current = 0; u32 pre_emphasis = 0; /* Set to a known-good pre-calibrated setting */ switch (sor->link_cfg->link_bw) { case SOR_LINK_SPEED_G1_62: case SOR_LINK_SPEED_G2_7: drive_current = 0x13131313; pre_emphasis = 0; break; case SOR_LINK_SPEED_G5_4: printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n"); default: printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", sor->link_cfg->link_bw); return; } tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), drive_current); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); }
static void dump_sor_reg(struct tegra_dc_sor_data *sor) { #define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \ #a, a, tegra_sor_readl(sor, a)); DUMP_REG(NV_SOR_SUPER_STATE0); DUMP_REG(NV_SOR_SUPER_STATE1); DUMP_REG(NV_SOR_STATE0); DUMP_REG(NV_SOR_STATE1); DUMP_REG(NV_HEAD_STATE0(0)); DUMP_REG(NV_HEAD_STATE0(1)); DUMP_REG(NV_HEAD_STATE1(0)); DUMP_REG(NV_HEAD_STATE1(1)); DUMP_REG(NV_HEAD_STATE2(0)); DUMP_REG(NV_HEAD_STATE2(1)); DUMP_REG(NV_HEAD_STATE3(0)); DUMP_REG(NV_HEAD_STATE3(1)); DUMP_REG(NV_HEAD_STATE4(0)); DUMP_REG(NV_HEAD_STATE4(1)); DUMP_REG(NV_HEAD_STATE5(0)); DUMP_REG(NV_HEAD_STATE5(1)); DUMP_REG(NV_SOR_CRC_CNTRL); DUMP_REG(NV_SOR_CLK_CNTRL); DUMP_REG(NV_SOR_CAP); DUMP_REG(NV_SOR_PWR); DUMP_REG(NV_SOR_TEST); DUMP_REG(NV_SOR_PLL0); DUMP_REG(NV_SOR_PLL1); DUMP_REG(NV_SOR_PLL2); DUMP_REG(NV_SOR_PLL3); DUMP_REG(NV_SOR_CSTM); DUMP_REG(NV_SOR_LVDS); DUMP_REG(NV_SOR_CRCA); DUMP_REG(NV_SOR_CRCB); DUMP_REG(NV_SOR_SEQ_CTL); DUMP_REG(NV_SOR_LANE_SEQ_CTL); DUMP_REG(NV_SOR_SEQ_INST(0)); DUMP_REG(NV_SOR_SEQ_INST(1)); DUMP_REG(NV_SOR_SEQ_INST(2)); DUMP_REG(NV_SOR_SEQ_INST(3)); DUMP_REG(NV_SOR_SEQ_INST(4)); DUMP_REG(NV_SOR_SEQ_INST(5)); DUMP_REG(NV_SOR_SEQ_INST(6)); DUMP_REG(NV_SOR_SEQ_INST(7)); DUMP_REG(NV_SOR_SEQ_INST(8)); DUMP_REG(NV_SOR_PWM_DIV); DUMP_REG(NV_SOR_PWM_CTL); DUMP_REG(NV_SOR_MSCHECK); DUMP_REG(NV_SOR_XBAR_CTRL); DUMP_REG(NV_SOR_DP_LINKCTL(0)); DUMP_REG(NV_SOR_DP_LINKCTL(1)); DUMP_REG(NV_SOR_DC(0)); DUMP_REG(NV_SOR_DC(1)); DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0)); DUMP_REG(NV_SOR_PR(0)); DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0)); DUMP_REG(NV_SOR_POSTCURSOR(0)); DUMP_REG(NV_SOR_DP_CONFIG(0)); DUMP_REG(NV_SOR_DP_CONFIG(1)); DUMP_REG(NV_SOR_DP_MN(0)); DUMP_REG(NV_SOR_DP_MN(1)); DUMP_REG(NV_SOR_DP_PADCTL(0)); DUMP_REG(NV_SOR_DP_PADCTL(1)); DUMP_REG(NV_SOR_DP_DEBUG(0)); DUMP_REG(NV_SOR_DP_DEBUG(1)); DUMP_REG(NV_SOR_DP_SPARE(0)); DUMP_REG(NV_SOR_DP_SPARE(1)); DUMP_REG(NV_SOR_DP_TPG); return; }