if (aio->aio_loc.loc_port != AWINIOCF_PORT_DEFAULT)
aprint_normal(" port %d", aio->aio_loc.loc_port);
return QUIET;
}
#define OFFANDSIZE(n) AWIN_##n##_OFFSET, (AWIN_##n##_OFFSET < 0x20000 ? 0x1000 : 0x400)
#define NOPORT AWINIOCF_PORT_DEFAULT
#define NOINTR AWINIO_INTR_DEFAULT
#define AANY 0
#define A10 AWINIO_ONLY_A10
#define A20 AWINIO_ONLY_A20
#define REQ AWINIO_REQUIRED
static const struct awin_locators awin_locators[] = {
{ "awinicu", OFFANDSIZE(INTC), NOPORT, NOINTR, A10|REQ },
{ "awingpio", OFFANDSIZE(PIO), NOPORT, NOINTR, AANY|REQ },
{ "awintmr", OFFANDSIZE(TMR), NOPORT, AWIN_IRQ_TMR0, A10 },
{ "com", OFFANDSIZE(UART0), 0, AWIN_IRQ_UART0, AANY },
{ "com", OFFANDSIZE(UART1), 1, AWIN_IRQ_UART1, AANY },
{ "com", OFFANDSIZE(UART2), 2, AWIN_IRQ_UART2, AANY },
{ "com", OFFANDSIZE(UART3), 3, AWIN_IRQ_UART3, AANY },
{ "com", OFFANDSIZE(UART4), 4, AWIN_IRQ_UART4, AANY },
{ "com", OFFANDSIZE(UART5), 5, AWIN_IRQ_UART5, AANY },
{ "com", OFFANDSIZE(UART6), 6, AWIN_IRQ_UART6, AANY },
{ "com", OFFANDSIZE(UART7), 7, AWIN_IRQ_UART7, AANY },
{ "awinwdt", OFFANDSIZE(TMR), NOPORT, NOINTR, AANY },
{ "awinusb", OFFANDSIZE(USB1), 0, NOINTR, AANY },
{ "awinusb", OFFANDSIZE(USB2), 1, NOINTR, AANY },
{ "sdhc", OFFANDSIZE(SDMMC0), 0, AWIN_IRQ_SDMMC0, AANY },
{ "sdhc", OFFANDSIZE(SDMMC1), 1, AWIN_IRQ_SDMMC1, AANY },
return QUIET;
}
#define OFFANDSIZE(n) AWIN_##n##_OFFSET, (AWIN_##n##_OFFSET < 0x20000 ? 0x1000 : 0x400)
#define NOPORT AWINIOCF_PORT_DEFAULT
#define NOINTR AWINIO_INTR_DEFAULT
#define AANY 0
#define A10 AWINIO_ONLY_A10
#define A20 AWINIO_ONLY_A20
#define A31 AWINIO_ONLY_A31
#define A80 AWINIO_ONLY_A80
#define REQ AWINIO_REQUIRED
static const struct awin_locators awin_locators[] = {
{ "awinicu", OFFANDSIZE(INTC), NOPORT, NOINTR, A10|REQ },
{ "awingpio", OFFANDSIZE(PIO), NOPORT, AWIN_IRQ_PIO, A10|A20|REQ },
{ "awingpio", OFFANDSIZE(PIO), NOPORT, NOINTR, A31|REQ },
{ "awingpio", OFFANDSIZE(A80_PIO), NOPORT, NOINTR, A80|REQ },
{ "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_IRQ_DMA, A10|A20 },
{ "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_A31_IRQ_DMA, A31 },
{ "awindma", OFFANDSIZE(A80_DMA), NOPORT, AWIN_A80_IRQ_DMA, A80 },
{ "awintmr", OFFANDSIZE(TMR), NOPORT, AWIN_IRQ_TMR0, A10 },
{ "awincnt", OFFANDSIZE(CPUCFG), NOPORT, NOINTR, A20 },
{ "awincnt", OFFANDSIZE(A31_CPUCFG), NOPORT, NOINTR, A31 },
{ "com", OFFANDSIZE(UART0), 0, AWIN_IRQ_UART0, A10|A20 },
{ "com", OFFANDSIZE(UART1), 1, AWIN_IRQ_UART1, A10|A20 },
{ "com", OFFANDSIZE(UART2), 2, AWIN_IRQ_UART2, A10|A20 },
{ "com", OFFANDSIZE(UART3), 3, AWIN_IRQ_UART3, A10|A20 },
{ "com", OFFANDSIZE(UART4), 4, AWIN_IRQ_UART4, A10|A20 },
{ "com", OFFANDSIZE(UART5), 5, AWIN_IRQ_UART5, A10|A20 },