void OS_InitHW(void) { OS_IncDI(); OS_ARM_CACHE_Sync(); // Ensure, caches are synchronized /* Initialize PIT as OS timer, enable timer + timer interrupt */ PIT_MR = ((OS_TIMER_RELOAD & 0x000FFFFF) | (1uL << 25) | (1uL << 24)); OS_ARM_InstallISRHandler(SYSTEM_IRQ_ID, _OS_SystemIrqhandler); OS_ARM_EnableISR(SYSTEM_IRQ_ID); OS_COM_Init(); OS_DecRI(); }
void OS_InitHW(void) { OS_DI(); _InitVIC(); /* Initialize interrupt controller */ /* Initialize PIT as embOS timer, enable timer + timer interrupt */ __PIT_MR = ((OS_TIMER_RELOAD & 0x000FFFFF) | (1 << 25) | (1 << 24)); OS_ARM_InstallISRHandler(_SYSTEM_IRQ_ID, _OS_SystemIrqhandler); OS_ARM_EnableISR(_SYSTEM_IRQ_ID); OS_COM_Init(); OS_RestoreI(); }
void OS_InitHW(void) { TCCR1A = (0<<6) // 0: No output |(0<<4) // 0: No output |(0<<0); // No PWM TCCR1B = (1<<7) // 0: Disable noise canceler |(0<<6) // X: Capture edge |(1<<3) // 1: Reset on compare match |(1<<0); // 1: clock source CK/1 OCR1A = (OS_FSYS/1000)-1; // generate 1ms interrupts TIMSK |= (1<<4); // Output CompareA Match Interrupt Enable OS_COM_Init(); // Initialize communication to embOS Viewer }
/********************************************************************* * * OS_InitHW() * * Initialize the hardware (timer) required for embOS to run. * May be modified, if an other timer should be used */ void OS_InitHW(void) { TCCR3A_COM3A1 = 0; // 0: No output TCCR3A_COM3A0 = 0; // 0: No output TCCR3A_WGM31 = 0; // 0: No PWM TCCR3A_WGM30 = 0; // 0: No PWM TCCR3B_ICNC3 = 0; // 0: Disable noise canceler TCCR3B_ICES3 = 0; // 0: capturee edge TCCR3B_ICNC3 = 0; // 0: Disable noise canceler TCCR3B_WGM32 = 1; // 1: Reset on compare match TCCR3B_CS32 = 0; // Clock-Source: 001 = CK/1 no prescaler TCCR3B_CS31 = 0; // Clock-Source: 010 = CK/8 TCCR3B_CS30 = 1; // Clock-Source: 001 = CK/1 OCR3A = (OS_FSYS/1000); // generate 1ms interrupts TIMSK3_OCIE3A = 1; // Output CompareA Match Interrupt Enable OS_COM_Init(); // Initialize communication to embOSView }