VOID AndesBhSchedule(RTMP_ADAPTER *ad) { struct MCU_CTRL *ctl = &ad->MCUCtrl; if (!OS_TEST_BIT(MCU_INIT, &ctl->flags)) return; if (((AndesQueueLen(ctl, &ctl->rx_doneq) > 0) || (AndesQueueLen(ctl, &ctl->tx_doneq) > 0)) && OS_TEST_BIT(MCU_INIT, &ctl->flags)) { #ifndef WORKQUEUE_BH RTMP_NET_TASK_DATA_ASSIGN(&ctl->cmd_msg_task, (unsigned long)(ad)); #ifdef ECOS_NETTASK_SCHDULE_NEW RTMP_OS_TASKLET_SCHE(MT_McuCommand); #else RTMP_OS_TASKLET_SCHE(&ctl->cmd_msg_task); #endif #else #ifdef ECOS_NETTASK_SCHDULE_NEW RTMP_OS_TASKLET_SCHE(MT_McuCommand); #else RTMP_OS_TASKLET_SCHE(&ctl->cmd_msg_task); #endif #endif } }
VOID AndesIncErrorCount(struct MCU_CTRL *ctl, enum cmd_msg_error_type type) { if (OS_TEST_BIT(MCU_INIT, &ctl->flags)) { switch (type) { case error_tx_kickout_fail: ctl->tx_kickout_fail_count++; break; case error_tx_timeout_fail: ctl->tx_timeout_fail_count++; break; case error_rx_receive_fail: ctl->rx_receive_fail_count++; break; default: MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("%s:unknown cmd_msg_error_type(%d)\n", __FUNCTION__, type)); } } }
VOID PciKickOutCmdMsgComplete(PNDIS_PACKET net_pkt) { struct cmd_msg *msg =CMD_MSG_CB(net_pkt)->msg; RTMP_ADAPTER *ad = (RTMP_ADAPTER *)msg->priv; struct MCU_CTRL *ctl = &ad->MCUCtrl; if (!OS_TEST_BIT(MCU_INIT, &ctl->flags)) return; if (!msg->need_wait) { AndesUnlinkCmdMsg(msg, &ctl->kickq); MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_INFO, ("%s: msg state = %d\n", __FUNCTION__, msg->state)); AndesQueueTailCmdMsg(&ctl->tx_doneq, msg, tx_done); } else { if (msg->state != tx_done) msg->state = wait_ack; } AndesBhSchedule(ad); }
VOID SdioKickOutCmdMsgComplete(struct cmd_msg *msg) { RTMP_ADAPTER *pAd = (RTMP_ADAPTER *)msg->priv; struct MCU_CTRL *ctl = &pAd->MCUCtrl; if (!OS_TEST_BIT(MCU_INIT, &ctl->flags)) return; if (!msg->need_wait) { AndesUnlinkCmdMsg(msg, &ctl->kickq); DBGPRINT(RT_DEBUG_INFO, ("%s: msg state = %d\n", __FUNCTION__, msg->state)); AndesQueueTailCmdMsg(&ctl->tx_doneq, msg, tx_done); } else { msg->state = wait_ack; } AndesBhSchedule(pAd); }
VOID AndesCmdMsgBh(unsigned long param) { RTMP_ADAPTER *ad = (RTMP_ADAPTER *)param; struct MCU_CTRL *ctl = &ad->MCUCtrl; struct cmd_msg *msg = NULL; while ((msg = AndesDequeueCmdMsg(ctl, &ctl->rx_doneq))) { switch (msg->state) { case rx_done: AndesRxProcessCmdMsg(ad, msg); AndesFreeCmdMsg(msg); break; case rx_receive_fail: AndesFreeCmdMsg(msg); break; default: AndesFreeCmdMsg(msg); MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("unknow msg state(%d)\n", msg->state)); break; } } while ((msg = AndesDequeueCmdMsg(ctl, &ctl->tx_doneq))) { switch (msg->state) { case tx_done: case tx_kickout_fail: case tx_timeout_fail: AndesFreeCmdMsg(msg); break; default: AndesFreeCmdMsg(msg); MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("unknow msg state(%d)\n", msg->state)); break; } } if (OS_TEST_BIT(MCU_INIT, &ctl->flags)) { AndesBhSchedule(ad); } }