static unsigned char
trix_read (int addr)
{
OUTB ((unsigned char) addr, 0x390); /* MT-0002-PC ASIC address */
return INB (0x391); /* MT-0002-PC ASIC data */
}
void VIA_TVInit(ScrnInfoPtr pScrn)
{
TRIDENTPtr pTrident=TRIDENTPTR(pScrn);
unsigned char idx=0;
unsigned char i;
unsigned char protect;
unsigned char TV_CRTC[TVX_CRTC_NUM] =
{ 0xC0,0xD0,0xD1,0xD2,0xD3,0xE0,0xE3,0xE4,0xE5,
0xE6,0xE7,0xF0,0xF1,0xF6,0xFE,0xFF };
unsigned char TV_CH7005C_RegIdx[TV_CH7005C_TVREG_NUM]={
0X00,0X01,0X03,0X04,0X06,0X07,0X08,0X09,
0X0A,0X0B,0X0D,0X0E,0X10,0X11,0X13,0X14,
0X15,0X17,0X18,0X19,0X1A,0X1B,0X1C,0X1D,
0X1E,0X1F,0X20,0X21,0X3D
};
#ifdef DEBUG_CODE_TRACE
ErrorF("VIAB3D: VIA_TVInit:\n");
#endif
if (pScrn->currentMode->HDisplay==640 && pScrn->currentMode->VDisplay==480 && (pScrn->depth==8 || pScrn->depth==16) && pTrident->TVSignalMode == 0)
{
/* Overlay window 1 position OK */
ErrorF("VIAB3D: VIA_TVInit: TV Params 640x480x8(16) NTSC\n");
idx=0;
pTrident->OverrideHsync=-71;
pTrident->OverrideVsync=15;
}
else if (pScrn->currentMode->HDisplay==800 && pScrn->currentMode->VDisplay==600 && (pScrn->depth==8 || pScrn->depth==16) && pTrident->TVSignalMode == 0)
{
/* Overlay window 1 position OK */
ErrorF("VIAB3D: VIA_TVInit: TV Params 800x600x8(16) NTSC\n");
idx=1;
pTrident->OverrideHsync=-152;
pTrident->OverrideVsync=72;
}
else if (pScrn->currentMode->HDisplay==640 && pScrn->currentMode->VDisplay==480 && pScrn->depth==24 && pTrident->TVSignalMode == 0)
{
ErrorF("VIAB3D: VIA_TVInit: TV Params 640x480x32 NTSC\n");
idx=2;
pTrident->OverrideHsync=-65;
pTrident->OverrideVsync=14;
}
else if (pScrn->currentMode->HDisplay==800 && pScrn->currentMode->VDisplay==600 && pScrn->depth==24 && pTrident->TVSignalMode == 0)
{
ErrorF("VIAB3D: VIA_TVInit: TV Params 800x600x32 NTSC\n");
idx=3;
pTrident->OverrideHsync=-158;
pTrident->OverrideVsync=72;
}
else if (pScrn->currentMode->HDisplay==640 && pScrn->currentMode->VDisplay==480 && (pScrn->depth==8 || pScrn->depth==16) && pTrident->TVSignalMode == 1)
{
/* Overlay window 1 position OK */
ErrorF("VIAB3D: VIA_TVInit: TV Params 640x480x8(16) PAL\n");
idx=4;
pTrident->OverrideHsync=2;
pTrident->OverrideVsync=65;
}
else if (pScrn->currentMode->HDisplay==800 && pScrn->currentMode->VDisplay==600 && (pScrn->depth==8 || pScrn->depth==16) && pTrident->TVSignalMode == 1)
{
ErrorF("VIAB3D: VIA_TVInit: TV Params 800x600x8(16) PAL\n");
/* patch TV screen defection */
idx=5;
/* patch 800x600 screen defect */
OUTB(0x3d4,0x2f);
OUTB(0x3d5,0xbf);
pTrident->OverrideHsync=-145;
pTrident->OverrideVsync=43;
}
else if (pScrn->currentMode->HDisplay==640 && pScrn->currentMode->VDisplay==480 && pScrn->depth==24 && pTrident->TVSignalMode == 1)
{
ErrorF("VIAB3D: VIA_TVInit: TV Params 640x480x32 PAL\n");
idx=6;
pTrident->OverrideHsync=0;
pTrident->OverrideVsync=63;
}
else if (pScrn->currentMode->HDisplay==800 && pScrn->currentMode->VDisplay==600 && pScrn->depth==24 && pTrident->TVSignalMode == 1)
{
ErrorF("VIAB3D: VIA_TVInit: TV Params 800x600x32 PAL\n");
idx=7;
OUTB(0x3d4,0x2f);
OUTB(0x3d5,0xbf);
pTrident->OverrideHsync=-141;
pTrident->OverrideVsync=42;
}
else
{
ErrorF("VIAB3D: VIA_TVInit: TV Params default mode\n");
return;
}
/* Unprotect */
OUTB(0x3C4, 0x11);
protect = INB(0x3C5);
OUTB(0x3C5, 0x92);
/* Set TV hw environment */
OUTB(0x3c4,0x24);
OUTB(0x3c5,0x4f);
OUTB(0x3d4,0xc1);
OUTB(0x3d5,0x41);
OUTB(0x3ce,0x23);
OUTB(0x3cf,0x88);
/* set CRT + TV */
OUTB(0x3CE,0x33);
OUTB(0x3CF,0x20);
/* set CRTC */
for( i = 0; i < TVX_CRTC_NUM; i++ )
{
OUTB(0x3D4, TV_CRTC[i]);
if (pTrident->TVChipset==2) {
OUTB(0x3D5, TV_CH7005C_Table[idx][i]);
}
else {
OUTB(0x3D5, TVX_VT1621_Table[idx][i]);
}
}
/* Digital TV interface control */
switch (pTrident->TVChipset)
{
case 1: OUTB(0x3C4,0xD8);
OUTB(0x3C5,0x60);
OUTB(0x3C4,0xD9);
OUTB(0x3C5,0x38);
break;
case 2: OUTB(0x3c4,0xd8);
OUTB(0x3c5,0x24);
OUTB(0x3C4,0xD9);
OUTB(0x3C5,0x18);
break;
}
switch (pTrident->TVChipset)
{
case 1:
/* set TVX registers */
for (i=0; i < TVX_REG_NUM; i++ )
{
smbus_write(pScrn,TVX_VT1621_Table[idx][TVX_CRTC_NUM+i], i, TVX_VT1621_PORT);
}
break;
case 2:
for (i=0; i<TV_CH7005C_TVREG_NUM; i++)
{
smbus_write(pScrn,TV_CH7005C_Table[idx][TV_CH7005C_CRTC_NUM+i], TV_CH7005C_RegIdx[i], TV_CH7005C_PORT);
}
break;
}
/*VIA_DumpReg(pScrn);*/
/* protect */
OUTB(0x3C4, 0x11);
OUTB(0x3C5, protect);
}
static int
fm801intr (oss_device_t * osdev)
{
fm801_devc *devc = (fm801_devc *) osdev->devc;
unsigned int status;
int i;
int serviced = 0;
status = INB (devc->osdev, devc->base + IRQ_STATUS);
/* Playback interrupt */
if (status & 0x01)
{
serviced = 1;
for (i = 0; i < MAX_PORTC; i++)
{
fm801_portc *portc = &devc->portc[i];
if (portc->trigger_bits & PCM_ENABLE_OUTPUT)
{
dmap_t *dmapout = audio_engines[portc->audiodev]->dmap_out;
devc->play_count++;
if (devc->play_count == dmapout->nfrags)
devc->play_count = 0;
if (devc->play_flag)
{
OUTL (devc->osdev, dmapout->dmabuf_phys +
devc->play_count * dmapout->fragment_size,
devc->base + PLAY_BUF1_ADDR);
}
else
{
OUTL (devc->osdev, dmapout->dmabuf_phys +
devc->play_count * dmapout->fragment_size,
devc->base + PLAY_BUF2_ADDR);
}
devc->play_flag = !devc->play_flag;
oss_audio_outputintr (portc->audiodev, 1);
}
}
OUTB (devc->osdev, status | 0x01, devc->base + IRQ_STATUS);
}
/* Record Interrupt */
if (status & 0x02)
{
serviced = 1;
for (i = 0; i < MAX_PORTC; i++)
{
fm801_portc *portc = &devc->portc[i];
if (portc->trigger_bits & PCM_ENABLE_INPUT)
{
dmap_t *dmapin = audio_engines[portc->audiodev]->dmap_in;
devc->rec_count++;
if (devc->rec_count == dmapin->nfrags)
devc->rec_count = 0;
if (devc->rec_flag)
{
OUTL (devc->osdev, dmapin->dmabuf_phys +
devc->rec_count * dmapin->fragment_size,
devc->base + REC_BUF1_ADDR);
}
else
OUTL (devc->osdev, dmapin->dmabuf_phys +
devc->rec_count * dmapin->fragment_size,
devc->base + REC_BUF2_ADDR);
devc->rec_flag = !devc->rec_flag;
oss_audio_inputintr (portc->audiodev, 0);
}
}
OUTB (devc->osdev, status | 0x02, devc->base + IRQ_STATUS);
}
/* MIDI Interrupt */
if (status & 0x80)
{
serviced = 1;
/* uart401intr (INT_HANDLER_CALL (devc->mpu_irq)); */
OUTB (devc->osdev, status | 0x80, devc->base + IRQ_STATUS);
}
return serviced;
}
void
mute_sf16fmd2(int v) {
OUTB(radioport, v ? 0x04 : 0x00);
inbits(4);
}
static u8 pmio_read_index(u32 port_base, u8 reg)
{
OUTB(reg, port_base);
return INB(port_base + 1);
}
static int send_pcb(elp_device * adapter, pcb_struct * pcb)
{
int i;
int cont;
int retry = 0;
int timeout;
CHECK_NULL(pcb);
CHECK_NULL(adapter);
if (pcb->length > MAX_PCB_DATA)
printk(invalid_pcb_msg, pcb->length, filename, __LINE__);
while (1) {
cont = 1;
/*
* load each byte into the command register and
* wait for the HCRE bit to indicate the adapter
* had read the byte
*/
SET_HSF(0);
OUTB(pcb->command, (adapter->io_addr)+PORT_COMMAND);
cont = WAIT_HCRE(5);
if (cont) {
OUTB(pcb->length, (adapter->io_addr)+PORT_COMMAND);
cont = WAIT_HCRE(2);
}
for (i = 0; cont && (i < pcb->length); i++) {
OUTB(pcb->data.raw[i], (adapter->io_addr)+PORT_COMMAND);
cont = WAIT_HCRE(2);
}
/* set the host status bits to indicate end of PCB */
/* send the total packet length as well */
/* wait for the adapter to indicate that it has read the PCB */
if (cont) {
SET_HSF(HSF_PCB_END);
OUTB(2+pcb->length, adapter->io_addr+PORT_COMMAND);
timeout = jiffies + 6;
while (jiffies < timeout) {
i = GET_ASF();
if ((i == ASF_PCB_ACK) ||
(i == ASF_PCB_NAK))
break;
}
if (jiffies >= timeout)
TIMEOUT_MSG();
if (i == ASF_PCB_ACK) {
SET_HSF(0);
return TRUE;
} else if (i == ASF_PCB_NAK) {
SET_HSF(0);
printk("%s: PCB send was NAKed\n", adapter->name);
{
int to = jiffies + 5;
while (jiffies < to)
;
}
}
}
if (elp_debug >= 2)
printk("%s: NAK/timeout on send PCB\n", adapter->name);
if ((retry++ & 7) == 0)
printk("%s: retry #%i on send PCB\n", adapter->name, retry);
}
return FALSE;
}
static int elp_open (struct device *dev)
{
elp_device * adapter = (elp_device *) dev->priv;
CHECK_NULL(dev);
if (elp_debug >= 3)
printk("%s: request to open device\n", dev->name);
/*
* make sure we actually found the device
*/
if (adapter == NULL) {
printk("%s: Opening a non-existent physical device\n", dev->name);
return -EAGAIN;
}
/*
* disable interrupts on the board
*/
OUTB(0x00, adapter->io_addr+PORT_CONTROL);
/*
* clear any pending interrupts
*/
INB(adapter->io_addr+PORT_COMMAND);
/*
* interrupt routine not entered
*/
dev->interrupt = 0;
/*
* transmitter not busy
*/
dev->tbusy = 0;
/*
* install our interrupt service routine
*/
if (request_irq(dev->irq, &elp_interrupt, 0, "3c505"))
return -EAGAIN;
/*
* make sure we can find the device header given the interrupt number
*/
irq2dev_map[dev->irq] = dev;
/*
* enable interrupts on the board
*/
OUTB(CONTROL_CMDE, adapter->io_addr+PORT_CONTROL);
/*
* device is now officially open!
*/
dev->start = 1;
/*
* configure adapter memory: we need 10 multicast addresses, default==0
*/
if (elp_debug >= 3)
printk("%s: sending 3c505 memory configuration command\n", dev->name);
adapter->tx_pcb.command = CMD_CONFIGURE_ADAPTER_MEMORY;
adapter->tx_pcb.data.memconf.cmd_q = 10;
adapter->tx_pcb.data.memconf.rcv_q = 20;
adapter->tx_pcb.data.memconf.mcast = 10;
adapter->tx_pcb.data.memconf.frame = 20;
adapter->tx_pcb.data.memconf.rcv_b = 20;
adapter->tx_pcb.data.memconf.progs = 0;
adapter->tx_pcb.length = sizeof(struct Memconf);
adapter->got[CMD_CONFIGURE_ADAPTER_MEMORY] = 0;
if (!send_pcb(adapter, &adapter->tx_pcb))
printk("%s: couldn't send memory configuration command\n", dev->name);
else {
int timeout = jiffies + TIMEOUT;
while (adapter->got[CMD_CONFIGURE_ADAPTER_MEMORY] == 0 && jiffies < timeout)
;
if (jiffies >= timeout)
TIMEOUT_MSG();
}
/*
* configure adapter to receive broadcast messages and wait for response
*/
if (elp_debug >= 3)
printk("%s: sending 82586 configure command\n", dev->name);
adapter->tx_pcb.command = CMD_CONFIGURE_82586;
adapter->tx_pcb.data.configure = NO_LOOPBACK | RECV_BROAD;
adapter->tx_pcb.length = 2;
adapter->got[CMD_CONFIGURE_82586] = 0;
if (!send_pcb(adapter, &adapter->tx_pcb))
printk("%s: couldn't send 82586 configure command\n", dev->name);
else {
int timeout = jiffies + TIMEOUT;
while (adapter->got[CMD_CONFIGURE_82586] == 0 && jiffies < timeout)
;
if (jiffies >= timeout)
TIMEOUT_MSG();
}
/*
* queue receive commands to provide buffering
*/
if (!start_receive(adapter, &adapter->tx_pcb))
printk("%s: start receive command failed \n", dev->name);
if (elp_debug >= 3)
printk("%s: start receive command sent\n", dev->name);
return 0; /* Always succeed */
}
//******************************************************************************
// Function: iiWriteMaskII(pB)
// Parameters: pB - pointer to board structure
//
// Returns: Nothing
//
// Description:
//
// Writes arbitrary value to the mask register.
//
// This version operates on IntelliPort-II - style FIFO's
//
//******************************************************************************
static void
iiWriteMaskII(i2eBordStrPtr pB, unsigned char value)
{
OUTB(pB->i2ePointer, SEL_MASK);
OUTB(pB->i2ePointer, value);
}
//******************************************************************************
// Function: iiWriteMaskIIEX(pB)
// Parameters: pB - pointer to board structure
//
// Returns: Nothing
//
// Description:
//
// Writes arbitrary value to the mask register.
//
// This version operates on IntelliPort-IIEX - style FIFO's
//
//******************************************************************************
static void
iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value)
{
OUTB(pB->i2eXMask, value);
}
//******************************************************************************
// Function: iiEnableMailIrqII(pB)
// Parameters: pB - pointer to board structure
//
// Returns: Nothing
//
// Description:
//
// Enables board to interrupt host (only) by writing to host's in-bound mailbox.
//
// This version operates on IntelliPort-II - style FIFO's
//
//******************************************************************************
static void
iiEnableMailIrqII(i2eBordStrPtr pB)
{
OUTB(pB->i2ePointer, SEL_MASK);
OUTB(pB->i2ePointer, ST_IN_MAIL);
}
//******************************************************************************
// Function: iiEnableMailIrqIIEX(pB)
// Parameters: pB - pointer to board structure
//
// Returns: Nothing
//
// Description:
//
// Enables board to interrupt host (only) by writing to host's in-bound mailbox.
//
// This version operates on IntelliPort-IIEX - style FIFO's
//
//******************************************************************************
static void
iiEnableMailIrqIIEX(i2eBordStrPtr pB)
{
OUTB(pB->i2eXMask, MX_IN_MAIL);
}
static void exit_conf_mode_ali(uint16_t port)
{
OUTB(0xbb, port);
}
static void enter_conf_mode_ali(uint16_t port)
{
OUTB(0x51, port);
OUTB(0x23, port);
}
static void
trix_write (int addr, int data)
{
OUTB ((unsigned char) addr, 0x390); /* MT-0002-PC ASIC address */
OUTB ((unsigned char) data, 0x391); /* MT-0002-PC ASIC data */
}
void exit_conf_mode_fintek_7777(uint16_t port)
{
OUTB(0xaa, port); /* Fintek */
}
static void set_bank(uint16_t port, uint8_t bank)
{
OUTB(0x4E, port);
OUTB(bank, port + 1);
}
int elplus_probe(struct device *dev)
{
elp_device adapter;
int i;
CHECK_NULL(dev);
/*
* setup adapter structure
*/
adapter.io_addr = dev->base_addr = elp_autodetect(dev);
if ( !adapter.io_addr )
return -ENODEV;
/*
* As we enter here from bootup, the adapter should have IRQs enabled,
* but we can as well enable them anyway.
*/
OUTB(INB(dev->base_addr+PORT_CONTROL) | CONTROL_CMDE,
dev->base_addr+PORT_CONTROL);
autoirq_setup(0);
/*
* use ethernet address command to probe for board in polled mode
* (this also makes us the IRQ that we need for automatic detection)
*/
adapter.tx_pcb.command = CMD_STATION_ADDRESS;
adapter.tx_pcb.length = 0;
if (!send_pcb (&adapter, &adapter.tx_pcb) ||
!receive_pcb(&adapter, &adapter.rx_pcb) ||
(adapter.rx_pcb.command != CMD_ADDRESS_RESPONSE) ||
(adapter.rx_pcb.length != 6)) {
printk("%s: not responding to first PCB\n", dev->name);
return -ENODEV;
}
if (dev->irq) { /* Is there a preset IRQ? */
if (dev->irq != autoirq_report(0)) {
printk("%s: Detected IRQ doesn't match user-defined one.\n",dev->name);
return -ENODEV;
}
/* if dev->irq == autoirq_report(0), all is well */
} else /* No preset IRQ; just use what we can detect */
dev->irq=autoirq_report(0);
switch (dev->irq) { /* Legal, sane? */
case 0:
printk("%s: No IRQ reported by autoirq_report().\n",dev->name);
printk("%s: Check the jumpers of your 3c505 board.\n",dev->name);
return -ENODEV;
case 1:
case 6:
case 8:
case 13:
printk("%s: Impossible IRQ %d reported by autoirq_report().\n",
dev->name,
dev->irq);
return -ENODEV;
}
/*
* Now we have the IRQ number so we can disable the interrupts from
* the board until the board is opened.
*/
OUTB(INB(dev->base_addr+PORT_CONTROL) & ~CONTROL_CMDE,
dev->base_addr+PORT_CONTROL);
/*
* copy ethernet address into structure
*/
for (i = 0; i < 6; i++)
dev->dev_addr[i] = adapter.rx_pcb.data.eth_addr[i];
/*
* print remainder of startup message
*/
#if (ELP_KERNEL_TYPE < 2)
printk("%s: 3c505 card found at I/O 0x%x using IRQ%d has address %s\n",
dev->name, dev->base_addr, dev->irq, eth_print(dev->dev_addr));
#else
printk("%s: 3c505 card found at I/O 0x%x using IRQ%d has address %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->name, dev->base_addr, dev->irq,
dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
#endif
/*
* initialise the device
*/
elp_init(dev);
return 0;
}
static uint8_t datareg(uint16_t port, uint8_t reg)
{
OUTB(reg, port);
return INB(port + 1);
}
static void receive_packet(struct device * dev,
elp_device * adapter,
int len)
{
register int i;
unsigned short * ptr;
short d;
int timeout;
int rlen;
struct sk_buff *skb;
/*
* allocate a buffer to put the packet into.
* (for kernels prior to 1.1.4 only)
*/
#if (ELP_KERNEL_TYPE < 2)
int sksize = sizeof(struct sk_buff) + len + 4;
#endif
CHECK_NULL(dev);
CHECK_NULL(adapter);
if (len <= 0 || ((len & ~1) != len))
if (elp_debug >= 3)
printk("*** bad packet len %d at %s(%d)\n",len,filename,__LINE__);
rlen = (len+1) & ~1;
#if (ELP_KERNEL_TYPE < 2)
skb = alloc_skb(sksize, GFP_ATOMIC);
#else
skb = alloc_skb(rlen, GFP_ATOMIC);
#endif
/*
* make sure the data register is going the right way
*/
OUTB(INB(adapter->io_addr+PORT_CONTROL)|CONTROL_DIR, adapter->io_addr+PORT_CONTROL);
/*
* if buffer could not be allocated, swallow it
*/
if (skb == NULL) {
for (i = 0; i < (rlen/2); i++) {
timeout = jiffies + TIMEOUT;
while ((INB(adapter->io_addr+PORT_STATUS)&STATUS_HRDY) == 0 &&
jiffies < timeout)
;
if (jiffies >= timeout)
TIMEOUT_MSG();
d = inw(adapter->io_addr+PORT_DATA);
}
adapter->stats.rx_dropped++;
} else {
skb->lock = 0;
skb->len = rlen;
skb->dev = dev;
/*
* for kernels before 1.1.4, the driver allocated the buffer
*/
#if (ELP_KERNEL_TYPE < 2)
skb->mem_len = sksize;
skb->mem_addr = skb;
#endif
/*
* now read the data from the adapter
*/
ptr = (unsigned short *)SKB_DATA;
for (i = 0; i < (rlen/2); i++) {
timeout = jiffies + TIMEOUT;
while ((INB(adapter->io_addr+PORT_STATUS)&STATUS_HRDY) == 0 &&
jiffies < timeout)
;
if (jiffies >= timeout)
{
printk("*** timeout at %s(%d) reading word %d of %d ***\n",
filename,__LINE__, i, rlen/2);
#if (ELP_KERNEL_TYPE < 2)
kfree_s(skb, sksize);
#else
kfree_s(skb, rlen);
#endif
return;
}
*ptr = inw(adapter->io_addr+PORT_DATA);
ptr++;
}
/*
* the magic routine "dev_rint" passes the packet up the
* protocol chain. If it returns 0, we can assume the packet was
* swallowed up. If not, then we are responsible for freeing memory
*/
IS_SKB(skb);
/*
* for kernels before 1.1.4, the driver allocated the buffer, so it had
* to free it
*/
#if (ELP_KERNEL_TYPE < 2)
if (dev_rint((unsigned char *)skb, rlen, IN_SKBUFF, dev) != 0) {
printk("%s: receive buffers full.\n", dev->name);
kfree_s(skb, sksize);
}
#else
netif_rx(skb);
#endif
}
OUTB(INB(adapter->io_addr+PORT_CONTROL)&(~CONTROL_DIR), adapter->io_addr+PORT_CONTROL);
}
uint8_t regval(uint16_t port, uint8_t reg)
{
OUTB(reg, port);
return INB(port + ((port == 0x3bd) ? 2 : 1)); /* 0x3bd is special. */
}
void
fdc37c93xdump(void)
{
int config, i, x;
config = Config;
OUTB(config, 0x55);
OUTB(config, 0x55);
OUTB(config+Index, 0x20);
x = inb(config+Data);
print("fdc37c93x: Device ID 0x%2.2uX\n", x);
OUTB(config+Index, 0x22);
x = inb(config+Data);
print("fdc37c93x: Power/Control 0x%2.2uX\n", x);
OUTB(config+Index, 0x07);
OUTB(config+Data, 0);
for(i = 0; fddregs[i]; i++){
OUTB(config+Index, fddregs[i]);
x = inb(config+Data);
print("FDD%2.2uX: 0x%2.2uX\n", fddregs[i], x);
}
OUTB(config+Index, 0x70);
OUTB(config+Data, 0x06);
OUTB(config+Index, 0x74);
OUTB(config+Data, 0x02);
OUTB(config+Index, 0x30);
OUTB(config+Data, 0x01);
OUTB(config, 0xAA);
}
void regwrite(uint16_t port, uint8_t reg, uint8_t val)
{
OUTB(reg, port);
OUTB(val, port + 1);
}
static void pmio_write_index(u32 port_base, u8 reg, u8 value)
{
OUTB(reg, port_base);
OUTB(value, port_base + 1);
}
void enter_conf_mode_winbond_fintek_ite_8787(uint16_t port)
{
OUTB(0x87, port);
OUTB(0x87, port);
}
void VIA_RestoreTVDependVGAReg(ScrnInfoPtr pScrn)
{
TRIDENTPtr pTrident=TRIDENTPTR(pScrn);
unsigned char protect;
unsigned char bTmp;
int i;
unsigned char VGA_RegIdx_about_TV[VGA_REGNUM_ABOUT_TV]={
0xD8,0XD9,/* SR */
0X33,/* GR */
0XC0,0XD0,0XD1,0XD2,0XD3,0XE0,0XE3,0XE4,0XE5,/* CR */
0XE6,0XE7,0XF0,0XF1,0XF6,0XFE,0XFF
};
unsigned char TV_CH7005C_RegIdx[TV_CH7005C_TVREG_NUM]={
0X00,0X01,0X03,0X04,0X06,0X07,0X08,0X09,
0X0A,0X0B,0X0D,0X0E,0X10,0X11,0X13,0X14,
0X15,0X17,0X18,0X19,0X1A,0X1B,0X1C,0X1D,
0X1E,0X1F,0X20,0X21,0X3D
};
/*ErrorF("VIAB3D: VIA_RestoreTVDependVGAReg:\n");*/
/* Unprotect */
OUTB(0x3C4, 0x11);
protect = INB(0x3C5);
OUTB(0x3C5, 0x92);
/* Set TV Hw environment */
OUTB(0x3d4,0xc1);
OUTB(0x3d5,0x41);
/* SR_d8,SR_d9 */
for (i=0; i<2; i++)
{
OUTB(0x3c4,VGA_RegIdx_about_TV[i]);
bTmp=pTrident->DefaultTVDependVGASetting[i];
OUTB(0x3c5,bTmp);
}
/* GR_33 */
OUTB(0x3ce,0x33);
bTmp=pTrident->DefaultTVDependVGASetting[2];
OUTB(0x3cf,bTmp);
/* CR_c0,d0,d1,d2,d3,e0,e3,e4,e5,e6,e7,f0,f1,f6,fe,ff */
for (i=3; i<VGA_REGNUM_ABOUT_TV; i++)
{
OUTB(0x3d4,VGA_RegIdx_about_TV[i]);
bTmp=pTrident->DefaultTVDependVGASetting[i];
OUTB(0x3d5,bTmp);
}
switch (pTrident->TVChipset)
{
case 1:
for (i=0; i<TVX_REG_NUM; i++)
{
bTmp=pTrident->DefaultTVDependVGASetting[VGA_REGNUM_ABOUT_TV+i];
smbus_write(pScrn,bTmp,i,TVX_VT1621_PORT);
}
break;
case 2:
for (i=0; i<TV_CH7005C_TVREG_NUM; i++)
{
bTmp=pTrident->DefaultTVDependVGASetting[VGA_REGNUM_ABOUT_TV+i];
smbus_write(pScrn,bTmp,TV_CH7005C_RegIdx[i],TV_CH7005C_PORT);
}
break;
default:
ErrorF("VIAB3D: VIA_SaveTVDepentVGAReg: Wrong Chipset setting\n");
break;
}
/* protect */
OUTB(0x3C4, 0x11);
OUTB(0x3C5, protect);
}
void exit_conf_mode_winbond_fintek_ite_8787(uint16_t port)
{
OUTB(0xaa, port); /* Fintek, Winbond */
regwrite(port, 0x02, 0x02); /* ITE */
}
void VIA_DumpReg(ScrnInfoPtr pScrn)
{
TRIDENTPtr pTrident=TRIDENTPTR(pScrn);
int i,j;
unsigned char bTmp;
unsigned char protect;
/* Unprotect */
OUTB(0x3C4, 0x11);
protect = INB(0x3C5);
OUTB(0x3C5, 0x92);
/* SR */
for (i=0; i<16; i++)
{
for (j=0; j<16; j++)
{
OUTB(0x3c4,(16*i+j));
bTmp=INB(0x3c5);
ErrorF("SR%02x=%02x ",(16*i+j),bTmp);
}
ErrorF("\n");
}
ErrorF("\n");
/* CR */
for (i=0; i<16; i++)
{
for (j=0; j<16; j++)
{
OUTB(0x3d4,(16*i+j));
bTmp=INB(0x3d5);
ErrorF("CR%02x=%02x ",(16*i+j),bTmp);
}
ErrorF("\n");
}
ErrorF("\n");
/* GR */
for (i=0; i<16; i++)
{
for (j=0; j<16; j++)
{
OUTB(0x3ce,(16*i+j));
bTmp=INB(0x3cf);
ErrorF("GR%02x=%02x ",(16*i+j),bTmp);
}
ErrorF("\n");
}
ErrorF("\n");
/* SM */
for (i=0; i<16; i++)
{
for (j=0; j<16; j++)
{
if (pTrident->TVChipset==2)
bTmp=smbus_read(pScrn,(16*i+j),TV_CH7005C_PORT);
else bTmp=smbus_read(pScrn,(16*i+j),TVX_VT1621_PORT);
ErrorF("SM%02x=%02x ",(16*i+j),bTmp);
}
ErrorF("\n");
}
ErrorF("\n");
/* protect */
OUTB(0x3C4, 0x11);
OUTB(0x3C5, protect);
}
void enter_conf_mode_fintek_7777(uint16_t port)
{
OUTB(0x77, port);
OUTB(0x77, port);
}
/* sbDevicesPorInitTable */
void sb700_devices_por_init(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = _pci_make_tag(0, 20, 0);
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
* This is an I/O address. The I/O address must be on 16-byte boundry. */
printk_info("set a-link bridge access address\n");
//pci_write_config32(dev, 0xf0, AB_INDX);
pci_write_config32(dev, 0xf0, 0x00000cd8);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
printk_info("To enable ab bif dam access\n");
axcfg_reg(0x04, 1 << 2, 1 << 2);
axindxc_reg(0x21, 0xff, 0);
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
printk_info("Enabling Non-Posted Memory Write for the K8 Platform\n");
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
printk_info("set smbus iobase\n");
//pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
//vga lycheng
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
printk_info("enable smbus controller interface\n");
byte = pci_read_config8(dev, 0xd2);
byte |= (1 << 0);
pci_write_config8(dev, 0xd2, byte);
#if 0
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
printk_info("enable smbus 1, ASF 2.0\n");
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
#endif
/* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
pci_write_config8(dev, 0x0a, 0x1);
pci_write_config8(dev, 0x0b, 0x6);
/* KB2RstEnable */
printk_info("KB2RstEnable\n");
pci_write_config8(dev, 0x40, 0xd4);
/* Enable ISA Address 0-960K decoding */
printk_info("Enable ISA address decoding\n");
pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
printk_info("Enable ISA address 0xc0000-0xdffff decode\n");
pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
printk_info("Enable decode cycles to IO controls\n");
byte = pci_read_config8(dev, 0x41);
byte &= 0x80;
byte |= 0x33;
pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
printk_info("Disabling Legacy USB Fast SMI\n");
byte = pci_read_config8(dev, 0x62);
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
/* Features Enable */
printk_info("Features Enable\n");
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
/* SerialIrq Control */
printk_info("SerialIrq Control\n");
pci_write_config8(dev, 0x69, 0x90);
/* Test Mode, PCIB_SReset_En Mask is set. */
pci_write_config8(dev, 0x6c, 0x20);
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
printk_info("IO Address Enable\n");
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
//#ifndef ENABLE_SATA
#if 1
/* TODO: set ide as primary, if you want to boot from IDE, you'd better set it.Or add a configuration line.*/
printk_info("set ide as primary\n");
byte = pci_read_config8(dev, 0xAD);
byte |= 0x1<<3;
byte &= ~(0x1<<4);
pci_write_config8(dev, 0xAD, byte);
/* This register is not used on sb700. It came from older chipset. */
/*pci_write_config8(dev, 0x95, 0xFF); */
#endif
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
printk_info("Set smbus iospace enable\n");
pci_write_config16(dev, 0x4, 0x0407);
#if 1
/* clear any lingering errors, so the transaction will run */
printk_info("IO Address Enable\n");
//OUTB(INB(0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT);
OUTB(INB(BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT), BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT);
#endif
/* IDE Device, BDF:0-20-1 */
printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
dev = _pci_make_tag(0, 20, 1);
/* Disable prefetch */
printk_info("Disable prefetch\n");
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
dev = _pci_make_tag(0, 20, 3);
/* DMA enable */
printk_info("DMA enable\n");
pci_write_config8(dev, 0x40, 0x04);
/* IO Port Decode Enable */
printk_info("IO Port Decode Enable\n");
pci_write_config8(dev, 0x44, 0xFF);
pci_write_config8(dev, 0x45, 0xFF);
pci_write_config8(dev, 0x46, 0xC3);
pci_write_config8(dev, 0x47, 0xFF);
/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
* Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
* Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
* Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
printk_info("IO/Mem Port Decode Enable\n");
byte = pci_read_config8(dev, 0x48);
byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
byte |= 1 << 6; /* enable for RTC I/O range */
pci_write_config8(dev, 0x48, byte);
pci_write_config8(dev, 0x49, 0xFF);
/* Enable 0x480-0x4bf, 0x4700-0x470B */
byte = pci_read_config8(dev, 0x4A);
byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
pci_write_config8(dev, 0x4A, byte);
/* Set LPC ROM size, it has been done in sb700_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
* pci_write_config16(dev, 0x68, 0x000e)
* pci_write_config16(dev, 0x6c, 0xfff0);*/
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
printk_info("Enable Tpm12_en and Tpm_legacy\n");
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
dev = _pci_make_tag(0, 20, 4);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
/* Arbiter enable. */
printk_info("Arbiter enable\n");
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into hight priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_write_config8(dev, 0x1c, 0x11);
* pci_write_config8(dev, 0x1d, 0x11);*/
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/
printk_info("CIM set this register\n");
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
printk_info("enable pcib_dual_en_up\n");
pci_write_config8(dev, 0x50, 0x01);
#ifdef ENABLE_SATA
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
printk_info("sb700_devices_por_init(): SATA Device, BDF:0-17-0\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
dev = _pci_make_tag(0, 17, 0);
/*PHY Global Control, we are using A14.
* default: 0x2c40 for ASIC revision A12 and below
* 0x2c00 for ASIC revision A13 and above.*/
printk_info("PHY Global Control\n");
pci_write_config16(dev, 0x86, 0x2C00);
#endif
}
void put_serial(UB val){
while((INB(DUARTx_UDSRn(1,1))&0x2)!=0);
OUTB(DUARTx_UTHRn(1,1), val);
}
