void
Mach64_ShowCursor(bool bShow)
{
// Turn cursor on/off.
OUTREGM(GEN_TEST_CNTL, bShow ? HWCURSOR_ENABLE : 0, HWCURSOR_ENABLE);
}
void
Rage128_ShowCursor(bool bShow)
{
// Turn cursor on/off.
OUTREGM(R128_CRTC_GEN_CNTL, bShow ? R128_CRTC_CUR_EN : 0, R128_CRTC_CUR_EN);
}
status_t
Rage128_SetDisplayMode(const DisplayModeEx& mode)
{
// The code to actually configure the display.
// All the error checking must be done in ProposeDisplayMode(),
// and assume that the mode values we get here are acceptable.
DisplayParams params; // where computed parameters are saved
if (gInfo.sharedInfo->displayType == MT_VGA) {
// Chip is connected to a monitor via a VGA connector.
if ( ! CalculateCrtcRegisters(mode, params))
return B_BAD_VALUE;
if ( ! CalculatePLLRegisters(mode, params))
return B_BAD_VALUE;
if ( ! CalculateDDARegisters(mode, params))
return B_BAD_VALUE;
SetRegisters(params);
} else {
// Chip is connected to a laptop LCD monitor; or via a DVI interface.
uint16 vesaMode = GetVesaModeNumber(display_mode(mode), mode.bitsPerPixel);
if (vesaMode == 0)
return B_BAD_VALUE;
if (ioctl(gInfo.deviceFileDesc, ATI_SET_VESA_DISPLAY_MODE,
&vesaMode, sizeof(vesaMode)) != B_OK)
return B_ERROR;
}
Rage128_AdjustFrame(mode);
// Initialize the palette so that color depths > 8 bits/pixel will display
// the correct colors.
// Select primary monitor and enable 8-bit color.
OUTREGM(R128_DAC_CNTL, R128_DAC_8BIT_EN,
R128_DAC_PALETTE_ACC_CTL | R128_DAC_8BIT_EN);
OUTREG8(R128_PALETTE_INDEX, 0); // set first color index
for (int i = 0; i < 256; i++)
OUTREG(R128_PALETTE_DATA, (i << 16) | (i << 8) | i );
Rage128_EngineInit(mode);
return B_OK;
}
status_t
Mach64_SetDisplayMode(const DisplayModeEx& mode)
{
// The code to actually configure the display.
// All the error checking must be done in ProposeDisplayMode(),
// and assume that the mode values we get here are acceptable.
SharedInfo& si = *gInfo.sharedInfo;
if (si.displayType == MT_VGA) {
// Chip is connected to a monitor via a VGA connector.
SetCrtcRegisters(mode);
SetClockRegisters(mode);
if (si.chipType >= MACH64_264VTB)
SetDSPRegisters(mode);
} else {
// Chip is connected to a laptop LCD monitor; or via a DVI interface.
uint16 vesaMode = GetVesaModeNumber(display_mode(mode), mode.bitsPerPixel);
if (vesaMode == 0)
return B_BAD_VALUE;
status_t status = ioctl(gInfo.deviceFileDesc, ATI_SET_VESA_DISPLAY_MODE,
&vesaMode, sizeof(vesaMode));
if (status != B_OK)
return status;
}
Mach64_AdjustFrame(mode);
// Initialize the palette so that the various color depths will display
// the correct colors.
OUTREGM(DAC_CNTL, DAC_8BIT_EN, DAC_8BIT_EN);
OUTREG8(DAC_MASK, 0xff);
OUTREG8(DAC_W_INDEX, 0); // initial color index
for (int i = 0; i < 256; i++) {
OUTREG8(DAC_DATA, i);
OUTREG8(DAC_DATA, i);
OUTREG8(DAC_DATA, i);
}
Mach64_EngineInit(mode);
return B_OK;
}
void
Mach64_AdjustFrame(const DisplayModeEx& mode)
{
// Adjust start address in frame buffer.
SharedInfo& si = *gInfo.sharedInfo;
int address = (mode.v_display_start * mode.virtual_width
+ mode.h_display_start) * ((mode.bitsPerPixel + 1) / 8);
address &= ~0x07;
address += si.frameBufferOffset;
OUTREGM(CRTC_OFF_PITCH, address, 0xfffff);
return;
}
void
Rage128_SetIndexedColors(uint count, uint8 first, uint8* colorData, uint32 flags)
{
// Set the indexed color palette for 8-bit color depth mode.
(void)flags; // avoid compiler warning for unused arg
if (gInfo.sharedInfo->displayMode.space != B_CMAP8)
return ;
// Select primary monitor and enable 8-bit color.
OUTREGM(R128_DAC_CNTL, R128_DAC_8BIT_EN,
R128_DAC_PALETTE_ACC_CTL | R128_DAC_8BIT_EN);
OUTREG8(R128_PALETTE_INDEX, first); // set first color index
while (count--) {
OUTREG(R128_PALETTE_DATA, ((colorData[0] << 16) // red
| (colorData[1] << 8) // green
| colorData[2])); // blue
colorData += 3;
}
}
status_t
Rage128_SetDPMSMode(uint32 dpmsMode)
{
// Set the display into one of the Display Power Management modes,
// and return B_OK if successful, else return B_ERROR.
SharedInfo& si = *gInfo.sharedInfo;
TRACE("Rage128_SetDPMSMode() mode: %d, display type: %d\n", dpmsMode, si.displayType);
int mask = (R128_CRTC_DISPLAY_DIS
| R128_CRTC_HSYNC_DIS
| R128_CRTC_VSYNC_DIS);
switch (dpmsMode) {
case B_DPMS_ON:
// Screen: On; HSync: On, VSync: On.
OUTREGM(R128_CRTC_EXT_CNTL, 0, mask);
break;
case B_DPMS_STAND_BY:
// Screen: Off; HSync: Off, VSync: On.
OUTREGM(R128_CRTC_EXT_CNTL,
R128_CRTC_DISPLAY_DIS | R128_CRTC_HSYNC_DIS, mask);
break;
case B_DPMS_SUSPEND:
// Screen: Off; HSync: On, VSync: Off.
OUTREGM(R128_CRTC_EXT_CNTL,
R128_CRTC_DISPLAY_DIS | R128_CRTC_VSYNC_DIS, mask);
break;
case B_DPMS_OFF:
// Screen: Off; HSync: Off, VSync: Off.
OUTREGM(R128_CRTC_EXT_CNTL, mask, mask);
break;
default:
TRACE("Invalid DPMS mode %d\n", dpmsMode);
return B_ERROR;
}
if (si.displayType == MT_LAPTOP) {
uint32 genCtrl;
switch (dpmsMode) {
case B_DPMS_ON:
genCtrl = INREG(R128_LVDS_GEN_CNTL);
genCtrl |= R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON | R128_LVDS_DIGON;
genCtrl &= ~R128_LVDS_DISPLAY_DIS;
OUTREG(R128_LVDS_GEN_CNTL, genCtrl);
break;
case B_DPMS_STAND_BY:
case B_DPMS_SUSPEND:
case B_DPMS_OFF:
genCtrl = INREG(R128_LVDS_GEN_CNTL);
genCtrl |= R128_LVDS_DISPLAY_DIS;
OUTREG(R128_LVDS_GEN_CNTL, genCtrl);
snooze(10);
genCtrl &= ~(R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON | R128_LVDS_DIGON);
OUTREG(R128_LVDS_GEN_CNTL, genCtrl);
break;
default:
TRACE("Invalid DPMS mode %d\n", dpmsMode);
return B_ERROR;
}
}
if (gInfo.sharedInfo->displayType == MT_DVI) {
switch (dpmsMode) {
case B_DPMS_ON:
OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
| (R128_FP_FPON | R128_FP_TDMS_EN));
break;
case B_DPMS_STAND_BY:
case B_DPMS_SUSPEND:
case B_DPMS_OFF:
OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
& ~(R128_FP_FPON | R128_FP_TDMS_EN));
break;
default:
TRACE("Invalid DPMS mode %d\n", dpmsMode);
return B_ERROR;
}
}
return B_OK;
}
static void
SetRegisters(DisplayParams& params)
{
// Write the common registers (most will be set to zero).
//-------------------------------------------------------
OUTREGM(R128_FP_GEN_CNTL, R128_FP_BLANK_DIS, R128_FP_BLANK_DIS);
OUTREG(R128_OVR_CLR, 0);
OUTREG(R128_OVR_WID_LEFT_RIGHT, 0);
OUTREG(R128_OVR_WID_TOP_BOTTOM, 0);
OUTREG(R128_OV0_SCALE_CNTL, 0);
OUTREG(R128_MPP_TB_CONFIG, 0);
OUTREG(R128_MPP_GP_CONFIG, 0);
OUTREG(R128_SUBPIC_CNTL, 0);
OUTREG(R128_VIPH_CONTROL, 0);
OUTREG(R128_I2C_CNTL_1, 0);
OUTREG(R128_GEN_INT_CNTL, 0);
OUTREG(R128_CAP0_TRIG_CNTL, 0);
OUTREG(R128_CAP1_TRIG_CNTL, 0);
// If bursts are enabled, turn on discards and aborts.
uint32 busCntl = INREG(R128_BUS_CNTL);
if (busCntl & (R128_BUS_WRT_BURST | R128_BUS_READ_BURST)) {
busCntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
OUTREG(R128_BUS_CNTL, busCntl);
}
// Write the DDA registers.
//-------------------------
OUTREG(R128_DDA_CONFIG, params.dda_config);
OUTREG(R128_DDA_ON_OFF, params.dda_on_off);
// Write the CRTC registers.
//--------------------------
OUTREG(R128_CRTC_GEN_CNTL, params.crtc_gen_cntl);
OUTREGM(R128_DAC_CNTL, R128_DAC_MASK_ALL | R128_DAC_8BIT_EN,
~(R128_DAC_RANGE_CNTL | R128_DAC_BLANKING));
OUTREG(R128_CRTC_H_TOTAL_DISP, params.crtc_h_total_disp);
OUTREG(R128_CRTC_H_SYNC_STRT_WID, params.crtc_h_sync_strt_wid);
OUTREG(R128_CRTC_V_TOTAL_DISP, params.crtc_v_total_disp);
OUTREG(R128_CRTC_V_SYNC_STRT_WID, params.crtc_v_sync_strt_wid);
OUTREG(R128_CRTC_OFFSET, 0);
OUTREG(R128_CRTC_OFFSET_CNTL, 0);
OUTREG(R128_CRTC_PITCH, params.crtc_pitch);
// Write the PLL registers.
//-------------------------
OUTREGM(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, R128_PLL_DIV_SEL);
SetPLLReg(R128_VCLK_ECP_CNTL, R128_VCLK_SRC_SEL_CPUCLK, R128_VCLK_SRC_SEL_MASK);
SetPLLReg(R128_PPLL_CNTL, 0xffffffff,
R128_PPLL_RESET | R128_PPLL_ATOMIC_UPDATE_EN | R128_PPLL_VGA_ATOMIC_UPDATE_EN);
PLLWaitForReadUpdateComplete();
SetPLLReg(R128_PPLL_REF_DIV, params.ppll_ref_div, R128_PPLL_REF_DIV_MASK);
PLLWriteUpdate();
PLLWaitForReadUpdateComplete();
SetPLLReg(R128_PPLL_DIV_3, params.ppll_div_3,
R128_PPLL_FB3_DIV_MASK | R128_PPLL_POST3_DIV_MASK);
PLLWriteUpdate();
PLLWaitForReadUpdateComplete();
SetPLLReg(R128_HTOTAL_CNTL, 0);
PLLWriteUpdate();
SetPLLReg(R128_PPLL_CNTL, 0, R128_PPLL_RESET
| R128_PPLL_SLEEP
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN);
snooze(5000);
SetPLLReg(R128_VCLK_ECP_CNTL, R128_VCLK_SRC_SEL_PPLLCLK,
R128_VCLK_SRC_SEL_MASK);
}
