struct platform_device *__init at32_add_device_twi(unsigned int id) { struct platform_device *pdev; if (id != 0) return NULL; pdev = platform_device_alloc("atmel_twi", id); if (!pdev) return NULL; if (platform_device_add_resources(pdev, atmel_twi0_resource, ARRAY_SIZE(atmel_twi0_resource))) goto err_add_resources; select_peripheral(PA(6), PERIPH_A, 0); /* SDA */ select_peripheral(PA(7), PERIPH_A, 0); /* SDL */ atmel_twi0_pclk.dev = &pdev->dev; platform_device_add(pdev); return pdev; err_add_resources: platform_device_put(pdev); return NULL; }
void pade (gf_view<refreq> &gr, gf_view<imfreq> const &gw, int n_points, double freq_offset) { // make sure the GFs have the same structure //assert(gw.shape() == gr.shape()); // copy the tail. it doesn't need to conform to the pade approximant gr.singularity() = gw.singularity(); auto sh = gw.data().shape().front_pop(); int N1 = sh[0], N2 = sh[1]; for (int n1=0; n1<N1; n1++) { for (int n2=0; n2<N2; n2++) { arrays::vector<dcomplex> z_in(n_points); // complex points arrays::vector<dcomplex> u_in(n_points); // values at these points arrays::vector<dcomplex> a(n_points); // corresponding Pade coefficients for (int i=0; i < n_points; ++i) z_in(i) = gw.mesh()[i]; for (int i=0; i < n_points; ++i) u_in(i) = gw.on_mesh(i)(n1,n2); triqs::utility::pade_approximant PA(z_in,u_in); gr() = 0.0; for (auto om : gr.mesh()) { dcomplex e = om + dcomplex(0.0,1.0)*freq_offset; gr[om](n1,n2) = PA(e); } } } }
ANNcoord annSpread( // compute point spread along dimension ANNpointArray pa, // point array ANNidxArray pidx, // point indices int n, // number of points int d) // dimension to check { ANNcoord min = PA(0,d); // compute max and min coords ANNcoord max = PA(0,d); for (int i = 1; i < n; i++) { ANNcoord c = PA(i,d); if (c < min) min = c; else if (c > max) max = c; } return (max - min); // total spread is difference }
/************************************************ Get the bounding box of a set of points Params: pa : data points pidx : permutation index of data points no_dims: number of dimensions n : number of points bbox : bounding box (return) ************************************************/ void get_bounding_box_float(float *pa, uint32_t *pidx, int8_t no_dims, uint32_t n, float *bbox) { float cur; int8_t bbox_idx, i, j; uint32_t i2; /* Use first data point to initialize */ for (i = 0; i < no_dims; i++) { bbox[2 * i] = bbox[2 * i + 1] = PA(0, i); } /* Update using rest of data points */ for (i2 = 1; i2 < n; i2++) { for (j = 0; j < no_dims; j++) { bbox_idx = 2 * j; cur = PA(i2, j); if (cur < bbox[bbox_idx]) { bbox[bbox_idx] = cur; } else if (cur > bbox[bbox_idx + 1]) { bbox[bbox_idx + 1] = cur; } } } }
void annPlaneSplit( // split points by a plane ANNpointArray pa, // points to split ANNidxArray pidx, // point indices int n, // number of points int d, // dimension along which to split ANNcoord cv, // cutting value int &br1, // first break (values < cv) int &br2) // second break (values == cv) { int l = 0; int r = n-1; for(;;) { // partition pa[0..n-1] about cv while (l < n && PA(l,d) < cv) l++; while (r >= 0 && PA(r,d) >= cv) r--; if (l > r) break; PASWAP(l,r); l++; r--; } br1 = l; // now: pa[0..br1-1] < cv <= pa[br1..n-1] r = n-1; for(;;) { // partition pa[br1..n-1] about cv while (l < n && PA(l,d) <= cv) l++; while (r >= br1 && PA(r,d) > cv) r--; if (l > r) break; PASWAP(l,r); l++; r--; } br2 = l; // now: pa[br1..br2-1] == cv < pa[br2..n-1] }
void annMinMax( // compute min and max coordinates along dim ANNpointArray pa, // point array ANNidxArray pidx, // point indices int n, // number of points int d, // dimension to check ANNcoord &min, // minimum value (returned) ANNcoord &max) // maximum value (returned) { min = PA(0,d); // compute max and min coords max = PA(0,d); for (int i = 1; i < n; i++) { ANNcoord c = PA(i,d); if (c < min) min = c; else if (c > max) max = c; } }
static int onfi_probe_cmd_exec(struct onfi_probe_params *params, unsigned char* data_ptr, int data_len) { struct cmd_element *cmd_list_ptr = ce_array; struct cmd_element *cmd_list_ptr_start = ce_array; int num_desc = 0; uint32_t status = 0; int nand_ret = NANDC_RESULT_SUCCESS; uint8_t desc_flags = BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG; params->cfg.addr_loc_0 = 0; params->cfg.addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); params->cfg.addr_loc_0 |= NAND_RD_LOC_OFFSET(0); params->cfg.addr_loc_0 |= NAND_RD_LOC_SIZE(data_len); cmd_list_ptr = qpic_nand_add_onfi_probe_ce(params, cmd_list_ptr); /* Enqueue the desc for the above commands */ bam_add_one_desc(&bam, CMD_PIPE_INDEX, (unsigned char*)cmd_list_ptr_start, PA((addr_t)(uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), desc_flags); cmd_list_ptr_start = cmd_list_ptr; num_desc++; /* Add Data desc */ bam_add_desc(&bam, DATA_PRODUCER_PIPE_INDEX, (unsigned char *)PA((addr_t)data_ptr), data_len, BAM_DESC_INT_FLAG); /* Wait for the commands to be executed */ qpic_nand_wait_for_cmd_exec(num_desc); /* Read buffer status and check for errors. */ status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr++); if (qpic_nand_check_status(status)) { nand_ret = NANDC_RESULT_FAILURE; goto onfi_probe_exec_err; } /* Wait for data to be available */ qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); /* Check for errors */ nand_ret = qpic_nand_check_status(status); onfi_probe_exec_err: return nand_ret; }
int main() { Expr tcs[] = { cst( 0 ), cst( 1 ) }; PA( tcs[ 0 ] ); PA( tcs[ 1 ] ); PA( cst( 0 ) ); PA( cst( 1 ) ); PA( slice( cst( SI64( 0x01234567 ) ), 8, 32 ) ); Expr gfe = cst( SI64( 0x656667 ) ); PRINT( gfe ); PRINT( gfe.cst_data() ); PRINT( gfe.cst_data( 8 ) ); Expr pgfe = pointer_on( gfe ); PRINT( pgfe ); PRINT( pgfe.vat_data() ); PRINT( pgfe.vat_data( 8 ) ); PRINT( slice( gfe, 8, 32 ) ); PRINT( slice( gfe, 8, 32 ).cst_data() ); PRINT( slice( gfe, 8, 32 ).cst_data( 8 ) ); PRINT( pointer_on( slice( gfe, 8, 32 ) ) ); PRINT( pointer_on( slice( gfe, 8, 32 ) ).vat_data() ); PRINT( add( arch->bt_ptr(), pointer_on( gfe ), cst( 1l ) ) ); PRINT( val_at( add( arch->bt_ptr(), pointer_on( gfe ), cst( 1l ) ), 16 ) ); // Expr sa = syscall( cst( 6 ), 2, tcs, 32 ).ret; // Expr sb = syscall( cst( 6 ), 2, tcs, 32 ).ret; // PA( sa ); // PA( sb ); // Expr pa = pointer_on( tcs[ 0 ], 64 ); // Expr pb = pointer_on( tcs[ 0 ], 64 ); // PA( pa ); // PA( pb ); // PA( add( bt_SI32, cst( 10 ), cst( 20 ) ) ); // PA( rand( 64 ) ); // PA( slice( cst( SI64( 0x176548 ) ), 8, 32 ) ); // Expr struct_expr = concat( cst( 0x17 ), rand( 32 ) ); // PA( struct_expr ); // PA( slice( struct_expr, 0, 16 ) ); // PA( slice( struct_expr, 0, 32 ) ); // PA( slice( struct_expr, 32, 64 ) ); // PA( slice( struct_expr, 32, 63 ) ); // PA( val_at( pointer_on( cst( 0x32 ), 64 ), 32 ) ); // PA( pointer_on( val_at( cst( 0x32 ), 32 ), 32 ) ); }
void mcfslt_profile_init(void) { printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n", PROFILEHZ); setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq); /* Set up TIMER 2 as high speed profile clock */ __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT)); __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, PA(MCFSLT_SCR)); }
void ia64_env_setup(struct ia64_boot_param *boot_param, struct kexec_boot_params *params) { unsigned long len; efi_system_table_t *systab; efi_runtime_services_t *runtime; unsigned long *set_virtual_address_map; char *command_line = (char *)params->command_line; uint64_t command_line_len = params->command_line_len; struct ia64_boot_param *new_boot_param = (struct ia64_boot_param *) params->boot_param_base; memcpy(new_boot_param, boot_param, 4096); /* * patch efi_runtime->set_virtual_address_map to a dummy function * * The EFI specification mandates that set_virtual_address_map only * takes effect the first time that it is called, and that * subsequent calls will return error. By replacing it with a * dummy function the new OS can think it is calling it again * without either the OS or any buggy EFI implementations getting * upset. * * Note: as the EFI specification says that set_virtual_address_map * will only take affect the first time it is called, the mapping * can't be updated, and thus mapping of the old and new OS really * needs to be the same. */ len = __dummy_efi_function_end - __dummy_efi_function; memcpy(command_line + command_line_len, __dummy_efi_function, len); systab = (efi_system_table_t *)new_boot_param->efi_systab; runtime = (efi_runtime_services_t *)PA(systab->runtime); set_virtual_address_map = (unsigned long *)PA(runtime->set_virtual_address_map); *(set_virtual_address_map) = (unsigned long)(command_line + command_line_len); flush_icache_range(command_line + command_line_len, len); patch_efi_memmap(params, new_boot_param); new_boot_param->efi_memmap = params->efi_memmap_base; new_boot_param->command_line = params->command_line; new_boot_param->console_info.orig_x = 0; new_boot_param->console_info.orig_y = 0; new_boot_param->initrd_start = params->ramdisk_base; new_boot_param->initrd_size = params->ramdisk_size; new_boot_param->vmcode_start = params->vmcode_base; new_boot_param->vmcode_size = params->vmcode_size; }
void coldfire_profile_init(void) { printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", PROFILEHZ); /* Set up TIMER 2 as high speed profile clock */ __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR)); __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq); }
static uint32_t qpic_nand_fetch_id(struct flash_info *flash) { struct cmd_element *cmd_list_ptr = ce_array; struct cmd_element *cmd_list_ptr_start = ce_array; int num_desc = 0; uint32_t status; uint32_t id; uint32_t flash_cmd = NAND_CMD_FETCH_ID; uint32_t exec_cmd = 1; int nand_ret = NANDC_RESULT_SUCCESS; /* Issue the Fetch id command to the NANDc */ bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)flash_cmd, CE_WRITE_TYPE); cmd_list_ptr++; /* Execute the cmd */ bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)exec_cmd, CE_WRITE_TYPE); cmd_list_ptr++; /* Prepare the cmd desc for the above commands */ bam_add_one_desc(&bam, CMD_PIPE_INDEX, (unsigned char*)cmd_list_ptr_start, PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG); /* Keep track of the number of desc added. */ num_desc++; qpic_nand_wait_for_cmd_exec(num_desc); cmd_list_ptr_start = ce_array; cmd_list_ptr = ce_array; /* Read the status register */ status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr); /* Check for errors */ nand_ret = qpic_nand_check_status(status); if (nand_ret) { dprintf( CRITICAL, "Read ID cmd status failed\n"); goto qpic_nand_fetch_id_err; } /* Read the id */ id = qpic_nand_read_reg(NAND_READ_ID, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr); flash->id = id; flash->vendor = id & 0xff; flash->device = (id >> 8) & 0xff; flash->dev_cfg = (id >> 24) & 0xFF; flash->widebus = 0; flash->widebus &= (id >> 24) & 0xFF; flash->widebus = flash->widebus? 1: 0; qpic_nand_fetch_id_err: return nand_ret; }
int annSplitBalance( // determine balance factor of a split ANNpointArray pa, // points to split ANNidxArray pidx, // point indices int n, // number of points int d, // dimension along which to split ANNcoord cv) // cutting value { int n_lo = 0; for(int i = 0; i < n; i++) { // count number less than cv if (PA(i,d) < cv) n_lo++; } return n_lo - n/2; }
static int usb_write(void *buf, unsigned len) { int r; if (fastboot_state == STATE_ERROR) goto oops; req->buf = PA((addr_t)buf); req->length = len; req->complete = req_complete; r = udc_request_queue(in, req); if (r < 0) { dprintf(INFO, "usb_write() queue failed\n"); goto oops; } event_wait(&txn_done); if (txn_status < 0) { dprintf(INFO, "usb_write() transaction failed\n"); goto oops; } return req->length; oops: fastboot_state = STATE_ERROR; return -1; }
static uint32_t crypto_write_reg(struct bam_instance *bam_core, uint32_t reg_addr, uint32_t val, uint8_t flags) { uint32_t ret = 0; struct cmd_element cmd_list_ptr; ret = (uint32_t)bam_add_cmd_element(&cmd_list_ptr, reg_addr, val, CE_WRITE_TYPE); /* Enqueue the desc for the above command */ ret = bam_add_one_desc(bam_core, CRYPTO_WRITE_PIPE_INDEX, (unsigned char*)PA((addr_t)&cmd_list_ptr), BAM_CE_SIZE, BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | flags); if (ret) { dprintf(CRITICAL, "CRYPTO_WRITE_REG: Reg write failed. reg addr = %x\n", reg_addr); goto crypto_read_reg_err; } crypto_wait_for_cmd_exec(bam_core, 1, CRYPTO_WRITE_PIPE_INDEX); crypto_read_reg_err: return val; }
irqreturn_t mcfslt_profile_tick(int irq, void *dummy) { /* Reset Slice Timer 1 */ __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR)); if (current->pid) profile_tick(CPU_PROFILING); return IRQ_HANDLED; }
void setup_initial_mapping(void) { pte_t * const pg0_phys = PA(pg0); pte_t * const pg1_phys = PA(pg0); pde_t * const pgdir_phys = PA(pgdir); pte_t const pte_flags = PTE_P | PTE_W; pde_t const pde_flags = PDE_P | PDE_W; for (size_t index = 0; index != PT_SIZE; ++index) { *(pg0_phys + index) = (index * PAGE_SIZE) | pte_flags; *(pg1_phys + index) = (index * PAGE_SIZE) | pte_flags; } *(pgdir_phys + PD_INDEX(0)) = (pde_t)pg0_phys | pde_flags; *(pgdir_phys + PD_INDEX(VIRTUAL_ADDRESS_BASE)) = (pde_t)pg1_phys | pde_flags; }
/* * Use the other timer to provide high accuracy profiling info. */ irqreturn_t coldfire_profile_tick(int irq, void *dummy) { /* Reset ColdFire timer2 */ __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER)); if (current->pid) profile_tick(CPU_PROFILING); return IRQ_HANDLED; }
void annMedianSplit( ANNpointArray pa, // points to split ANNidxArray pidx, // point indices int n, // number of points int d, // dimension along which to split ANNcoord &cv, // cutting value int n_lo) // split into n_lo and n-n_lo { int l = 0; // left end of current subarray int r = n-1; // right end of current subarray while (l < r) { register int i = (r+l)/2; // select middle as pivot register int k; if (PA(i,d) > PA(r,d)) // make sure last > pivot PASWAP(i,r) PASWAP(l,i); // move pivot to first position ANNcoord c = PA(l,d); // pivot value i = l; k = r; for(;;) { // pivot about c while (PA(++i,d) < c) ; while (PA(--k,d) > c) ; if (i < k) PASWAP(i,k) else break; } PASWAP(l,k); // pivot winds up in location k if (k > n_lo) r = k-1; // recurse on proper subarray else if (k < n_lo) l = k+1; else break; // got the median exactly } if (n_lo > 0) { // search for next smaller item ANNcoord c = PA(0,d); // candidate for max int k = 0; // candidate's index for (int i = 1; i < n_lo; i++) { if (PA(i,d) > c) { c = PA(i,d); k = i; } } PASWAP(n_lo-1, k); // max among pa[0..n_lo-1] to pa[n_lo-1] } // cut value is midpoint value cv = (PA(n_lo-1,d) + PA(n_lo,d))/2.0; }
static uint32_t qpic_nand_read_reg(uint32_t reg_addr, uint8_t flags, struct cmd_element *cmd_list_ptr) { uint32_t val; bam_add_cmd_element(cmd_list_ptr, reg_addr, (uint32_t)PA((addr_t)&val), CE_READ_TYPE); /* Enqueue the desc for the above command */ bam_add_one_desc(&bam, CMD_PIPE_INDEX, (unsigned char*)PA((addr_t)cmd_list_ptr), BAM_CE_SIZE, BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG | flags); qpic_nand_wait_for_cmd_exec(1); return val; }
void annEnclRect( ANNpointArray pa, // point array ANNidxArray pidx, // point indices int n, // number of points int dim, // dimension ANNorthRect &bnds) // bounding cube (returned) { for (int d = 0; d < dim; d++) { // find smallest enclosing rectangle ANNcoord lo_bnd = PA(0,d); // lower bound on dimension d ANNcoord hi_bnd = PA(0,d); // upper bound on dimension d for (int i = 0; i < n; i++) { if (PA(i,d) < lo_bnd) lo_bnd = PA(i,d); else if (PA(i,d) > hi_bnd) hi_bnd = PA(i,d); } bnds.lo[d] = lo_bnd; bnds.hi[d] = hi_bnd; } }
struct platform_device *__init at32_add_device_mci(unsigned int id) { struct platform_device *pdev; if (id != 0) return NULL; pdev = platform_device_alloc("atmel_mci", id); if (!pdev) return NULL; if (platform_device_add_resources(pdev, atmel_mci0_resource, ARRAY_SIZE(atmel_mci0_resource))) goto err_add_resources; select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */ select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */ select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ atmel_mci0_pclk.dev = &pdev->dev; platform_device_add(pdev); return pdev; err_add_resources: platform_device_put(pdev); return NULL; }
void annEnclRect( ES_INFO* es_info, ANNpointArray pa, // point array ANNidxArray pidx, // point indices int n, // number of points int dim, // dimension ANNorthRect &bnds) // bounding cube (returned) { for (int d = 0; d < dim; d++) { // find smallest enclosing rectangle #if 1 // es code es_info->get_value_by_index(pidx[0]); #endif ANNcoord lo_bnd = PA(0,d); // lower bound on dimension d ANNcoord hi_bnd = PA(0,d); // upper bound on dimension d // printf("n[%d]\n", n); for (int i = 0; i < n; i++) { #if 1 // es code es_info->get_value_by_index(pidx[i]); #endif // printf("PA[%d,%d]\n", i, d); if (PA(i,d) < lo_bnd) { lo_bnd = PA(i,d); } else if (PA(i,d) > hi_bnd) { hi_bnd = PA(i,d); } } bnds.lo[d] = lo_bnd; bnds.hi[d] = hi_bnd; } }
struct platform_device *__init at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) { /* * Manage the chipselects as GPIOs, normally using the same pins * the SPI controller expects; but boards can use other pins. */ static u8 __initdata spi0_pins[] = { GPIO_PIN_PA(3), GPIO_PIN_PA(4), GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; static u8 __initdata spi1_pins[] = { GPIO_PIN_PB(2), GPIO_PIN_PB(3), GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; struct platform_device *pdev; switch (id) { case 0: pdev = &atmel_spi0_device; select_peripheral(PA(0), PERIPH_A, 0); /* MISO */ select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ at32_spi_setup_slaves(0, b, n, spi0_pins); break; case 1: pdev = &atmel_spi1_device; select_peripheral(PB(0), PERIPH_B, 0); /* MISO */ select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ at32_spi_setup_slaves(1, b, n, spi1_pins); break; default: return NULL; } spi_register_board_info(b, n); platform_device_register(pdev); return pdev; }
ANNcoord annSpread( // compute point spread along dimension ES_INFO* es_info, ANNpointArray pa, // point array ANNidxArray pidx, // point indices int n, // number of points int d) // dimension to check { #if 1 // es code es_info->get_value_by_index(pidx[0]); #endif ANNcoord min = PA(0,d); // compute max and min coords ANNcoord max = PA(0,d); for (int i = 1; i < n; i++) { #if 1 // es code es_info->get_value_by_index(pidx[i]); #endif ANNcoord c = PA(i,d); if (c < min) min = c; else if (c > max) max = c; } return (max - min); // total spread is difference }
void pade(GF_Bloc_ImFreq const & Gw, GF_Bloc_ReFreq & Ge, int N_Matsubara_Frequencies, double Freq_Offset) { check_have_same_structure (Gw,Ge,false,true); assert (Gw.mesh.index_min==0); assert (Ge.mesh.index_min==0); double Beta = Gw.Beta; double omegaShift = (Gw.Statistic==Fermion ? 1 : 0); Array<COMPLEX,1> z_in(N_Matsubara_Frequencies); firstIndex i; z_in = I*Pi/Beta*(2*i+omegaShift); // Just copy the tail. It doesn't need to conform to the Pade approximant. Gw.tail = Ge.tail; int N1 = Gw.N1, N2 = Gw.N2; for (int n1=1; n1<=N1;n1++) for (int n2=1; n2<=N2;n2++){ int N = Gw.mesh.len(); Array<COMPLEX,1> u_in(N_Matsubara_Frequencies); // Values at the Matsubara frequencies Array<COMPLEX,1> a(N_Matsubara_Frequencies); // Pade coefficients for(int i=0; i < N_Matsubara_Frequencies; ++i){ u_in(i) = (i < N ? Gw.data_const(n1,n2,i) : Gw.tail.eval(z_in(i))(n1,n2)); } Pade_approximant PA(z_in,u_in); int Ne = Ge.mesh.len(); Ge.zero(); for (int i=0; i < Ne; ++i) { COMPLEX e = Ge.mesh[i] + I*Freq_Offset; Ge.data(n1,n2,i) = PA(e); } } }
void annMinMax( // compute min and max coordinates along dim ES_INFO* es_info, ANNpointArray pa, // point array ANNidxArray pidx, // point indices int n, // number of points int d, // dimension to check ANNcoord &min, // minimum value (returned) ANNcoord &max) // maximum value (returned) { #if 1 // es code es_info->get_value_by_index(pidx[0]); #endif min = PA(0,d); // compute max and min coords max = PA(0,d); for (int i = 1; i < n; i++) { #if 1 // es code es_info->get_value_by_index(pidx[i]); #endif ANNcoord c = PA(i,d); if (c < min) min = c; else if (c > max) max = c; } }
static int usb_read(void *_buf, unsigned len) { int r; unsigned xfer; unsigned char *buf = _buf; int count = 0; if (fastboot_state == STATE_ERROR) goto oops; while (len > 0) { xfer = (len > MAX_USBFS_BULK_SIZE) ? MAX_USBFS_BULK_SIZE : len; req->buf = PA((addr_t)buf); req->length = xfer; req->complete = req_complete; r = udc_request_queue(out, req); if (r < 0) { dprintf(INFO, "usb_read() queue failed\n"); goto oops; } event_wait(&txn_done); if (txn_status < 0) { dprintf(INFO, "usb_read() transaction failed\n"); goto oops; } count += req->length; buf += req->length; len -= req->length; /* short transfer? */ if (req->length != xfer) break; } /* * Force reload of buffer from memory * since transaction is complete now. */ arch_invalidate_cache_range(_buf, count); return count; oops: fastboot_state = STATE_ERROR; return -1; }
/* TODO: check why both vld and cmd need to be written. */ void qpic_nand_onfi_probe_cleanup(uint32_t vld, uint32_t dev_cmd1) { struct cmd_element *cmd_list_ptr = ce_array; struct cmd_element *cmd_list_ptr_start = ce_array; bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD1, dev_cmd1, CE_WRITE_TYPE); cmd_list_ptr++; bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD_VLD, vld, CE_WRITE_TYPE); cmd_list_ptr++; /* Enqueue the desc for the above commands */ bam_add_one_desc(&bam, CMD_PIPE_INDEX, (unsigned char*)cmd_list_ptr_start, PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), BAM_DESC_UNLOCK_FLAG | BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG); qpic_nand_wait_for_cmd_exec(1); }
void fill_mem_map(struct multiboot_info *mbi) { struct multiboot_mmap_entry * const mmap_info = (struct multiboot_mmap_entry *)mbi->mmap_addr; size_t const length = mbi->mmap_length; struct multiboot_mmap_entry *entry = mmap_info; struct boot_params * const params = PA(&boot_params); struct memory_map * const map = ¶ms->mmap; size_t count = 0; while ((size_t)entry < (size_t)mmap_info + length) { map->chunk[count].addr = entry->addr; map->chunk[count].size = entry->len; map->chunk[count].type = entry->type; entry = (struct multiboot_mmap_entry *) ((size_t)entry + entry->size + sizeof(entry->size)); ++count; } map->entries = count; }