void Memory_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
/* our code only works on Intel chipsets so make sure here */
if (pci_config_read16(PCIADDR(0, 0x00, 0), 0x00) != 0x8086)
bootInfo->memDetect = false;
else
bootInfo->memDetect = true;
/* manually */
getBoolForKey(kUseMemDetectKey, &bootInfo->memDetect, &bootInfo->bootConfig);
if (bootInfo->memDetect)
{
if (dram_controller_dev != NULL)
{
// Rek: pci dev ram controller direct and fully informative scan ...
scan_dram_controller(dram_controller_dev);
}
//Azi: gone on Kabyl's smbios update - reminder
// unfortunately still necesary for some comp where spd cant read correct speed
// scan_memory(&Platform);
scan_spd(&Platform); // check Mek's implementation!
}
}
void Memory_PCIDevice_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id == PCI_CLASS_BRIDGE_HOST
&& (current->dev.addr == PCIADDR(0, 0, 0)))
{
dram_controller_dev = current;
}
}
void Memory_start(void)
{
if (pci_config_read16(PCIADDR(0, 0x00, 0), 0x00) != 0x8086)
return;
register_hook_callback("PCIDevice", &Memory_PCIDevice_hook);
register_hook_callback("ScanMemory", &Memory_hook);
register_hook_callback("isMemoryRegistred", &is_Memory_Registred_Hook);
}
/** scan mem for memory autodection purpose */
void scan_mem() {
static bool done = false;
if (done) return;
/* our code only works on Intel chipsets so make sure here */
if (pci_config_read16(PCIADDR(0, 0x00, 0), 0x00) != 0x8086)
bootInfo->memDetect = false;
else
bootInfo->memDetect = true;
/* manually */
getBoolForKey(kUseMemDetect, &bootInfo->memDetect, &bootInfo->chameleonConfig);
if (bootInfo->memDetect) {
if (dram_controller_dev != NULL) {
scan_dram_controller(dram_controller_dev); // Rek: pci dev ram controller direct and fully informative scan ...
}
scan_spd(&Platform);
}
done = true;
}
void setup_pci_devs(pci_dt_t *pci_dt)
{
char *devicepath;
bool do_eth_devprop, do_gfx_devprop, do_enable_hpet, do_igp_devprop;
pci_dt_t *current = pci_dt;
do_eth_devprop = do_gfx_devprop = do_enable_hpet = false;
getBoolForKey(kEthernetBuiltIn, &do_eth_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kIGPEnabler, &do_igp_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->chameleonConfig);
while (current)
{
devicepath = get_pci_dev_path(current);
switch (current->class_id)
{
case PCI_CLASS_BRIDGE_HOST:
if (current->dev.addr == PCIADDR(0, 0, 0))
dram_controller_dev = current;
break;
case PCI_CLASS_NETWORK_ETHERNET:
if (do_eth_devprop)
set_eth_builtin(current);
break;
case PCI_CLASS_DISPLAY_VGA:
if (do_gfx_devprop){
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
setup_ati_devprop(current);
break;
case PCI_VENDOR_ID_INTEL:
setup_gma_devprop(current);
break;
case PCI_VENDOR_ID_NVIDIA:
setup_nvidia_devprop(current);
break;
}
break;
} else if (do_igp_devprop){
setup_gma_devprop(current);
break;
}
case PCI_CLASS_SERIAL_USB:
notify_usb_dev(current);
break;
case PCI_CLASS_BRIDGE_ISA:
if (do_enable_hpet)
force_enable_hpet(current);
break;
}
execute_hook("PCIDevice", current, NULL, NULL, NULL);
setup_pci_devs(current->children);
current = current->next;
}
}
void setup_pci_devs(pci_dt_t *pci_dt)
{
char *devicepath;
bool do_gfx_devprop = false;
bool do_skip_n_devprop = false;
bool do_skip_a_devprop = false;
bool do_skip_i_devprop = false;
bool do_enable_hpet = false;
bool do_hda_devprop = false;
pci_dt_t *current = pci_dt;
// GraphicsEnabler
getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->chameleonConfig);
// Skip keys
getBoolForKey(kSkipNvidiaGfx, &do_skip_n_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kSkipAtiGfx, &do_skip_a_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kSkipIntelGfx, &do_skip_i_devprop, &bootInfo->chameleonConfig);
// HDAEnable
getBoolForKey(kHDAEnabler, &do_hda_devprop, &bootInfo->chameleonConfig);
// ForceHPET
getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->chameleonConfig);
while (current)
{
devicepath = get_pci_dev_path(current);
switch (current->class_id)
{
case PCI_CLASS_BRIDGE_HOST:
DBG("Setup BRIDGE_HOST \n");
if (current->dev.addr == PCIADDR(0, 0, 0))
{
dram_controller_dev = current;
}
break; // PCI_CLASS_BRIDGE_HOST
case PCI_CLASS_NETWORK_ETHERNET:
DBG("Setup ETHERNET %s enabled\n", do_eth_devprop? "is":"is not");
verbose("[ ETHERNET DEVICE INFO ]\n");
setup_eth_devdrop(current);
verbose("\n");
break; // PCI_CLASS_NETWORK_ETHERNET
case PCI_CLASS_NETWORK_OTHER:
DBG("Setup WIRELESS %s enabled\n", do_wifi_devprop? "is":"is not");
verbose("[ WIRELESS DEVICE INFO ]\n");
setup_wifi_devdrop(current);
verbose("\n");
break; // PCI_CLASS_NETWORK_OTHER
case PCI_CLASS_DISPLAY_VGA:
DBG("GraphicsEnabler %s enabled\n", do_gfx_devprop? "is":"is not");
if (do_gfx_devprop)
{
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
if ( do_skip_a_devprop )
{
verbose("Skip ATi/AMD gfx device!\n");
}
else
{
verbose("[ ATi GFX DEVICE INFO ]\n");
setup_ati_devprop(current);
verbose("\n");
}
break; // PCI_VENDOR_ID_ATI
case PCI_VENDOR_ID_INTEL:
if ( do_skip_i_devprop )
{
verbose("Skip Intel gfx device!\n");
}
else
{
verbose("[ INTEL GMA DEVICE INFO ]\n");
setup_gma_devprop(current);
verbose("\n");
}
break; // PCI_VENDOR_ID_INTEL
case PCI_VENDOR_ID_NVIDIA:
if ( do_skip_n_devprop )
{
verbose("Skip Nvidia gfx device!\n");
}
else
{
verbose("[ NVIDIA GFX DEVICE INFO ]\n");
setup_nvidia_devprop(current);
verbose("\n");
}
break; // PCI_VENDOR_ID_NVIDIA
default:
break;
}
}
break; // PCI_CLASS_DISPLAY_VGA
case PCI_CLASS_MULTIMEDIA_AUDIO_DEV:
DBG("Setup HDEF %s enabled\n", do_hda_devprop ? "is":"is not");
if (do_hda_devprop)
{
verbose("[ AUDIO DEVICE INFO ]\n");
setup_hda_devprop(current);
verbose("\n");
}
break; // PCI_CLASS_MULTIMEDIA_AUDIO_DEV
case PCI_CLASS_SERIAL_USB:
DBG("USB\n");
notify_usb_dev(current);
break; // PCI_CLASS_SERIAL_USB
case PCI_CLASS_SERIAL_FIREWIRE:
DBG("FireWire\n");
verbose("[ FIREWIRE DEVICE INFO ]\n");
verbose("\tClass code: [%04X]\n\tFireWire device [%04x:%04x]-[%04x:%04x]\n\t%s\n",
current->class_id,current->vendor_id, current->device_id,
current->subsys_id.subsys.vendor_id,
current->subsys_id.subsys.device_id, devicepath);
// set_fwr_devdrop(current);
verbose("\n");
break; // PCI_CLASS_SERIAL_FIREWIRE
case PCI_CLASS_BRIDGE_ISA:
DBG("Force HPET %s enabled\n", do_enable_hpet ? "is":"is not");
if (do_enable_hpet)
{
verbose("[ HPET ]\n");
force_enable_hpet(current);
verbose("\n");
}
break; // PCI_CLASS_BRIDGE_ISA
}
execute_hook("PCIDevice", current, NULL, NULL, NULL);
DBG("setup_pci_devs current device ID = [%04x:%04x]\n", current->vendor_id, current->device_id);
setup_pci_devs(current->children);
current = current->next;
}
}
bool getSMBOemProcessorBusSpeed(returnType *value)
{
if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_DOTHAN: // Intel Pentium M
case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM: // Intel Atom (45nm)
return false;
case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7
{
// thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
value->word = qpibusspeed;
return true;
}
}
}
}
}
return false;
}
static int sm_get_bus_speed (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_PENTIUM_M: // Pentium M 0x0D
case CPU_MODEL_YONAH: // Yonah 0x0E
case CPU_MODEL_MEROM: // Merom 0x0F
case CPU_MODEL_PENRYN: // Penryn 0x17
case CPU_MODEL_ATOM: // Atom 45nm 0x1C
return 0; // TODO: populate bus speed for these processors
// case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
// if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
// return 2500; // Core i5
// return 4800; // Core i7
// case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
// case CPU_MODEL_NEHALEM_EX:
// case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
// return 4800; // GT/s / 1000
//
case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0; // TODO: populate bus speed for these processors
// case 0x19: // Intel Core i5 650 @3.20 Ghz
// return 2500; // why? Intel spec says 2.5GT/s
case 0x19: // Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
{ // thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
return qpibusspeed;
}
}
}
}
}
return 0;
}
bool getSMBOemProcessorBusSpeed(returnType *value)
{
if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel
switch (Platform.CPU.Family) {
case 0x06:
{
switch (Platform.CPU.Model) {
case CPU_MODEL_PENTIUM_M:
case CPU_MODEL_DOTHAN: // Intel Pentium M
case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM: // Intel Atom (45nm)
return false;
case 0x19:
case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7
// case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) // MacMan removed not valid for this CPU
// case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) // MacMan removed not valid for this CPU
// case CPU_MODEL_IVYBRIDGE_XEON: // MacMan moved
// case CPU_MODEL_HASWELL: // MacMan removed not valid for this CPU
// case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)// MacMan moved
{
// thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
unsigned int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00) {
nhm_bus = possible_nhm_bus[i];
}
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0) {
qpibusspeed = ((qpibusspeed+50)/100)*100;
}
DBG("qpibusspeed %d\n", qpibusspeed);
value->word = qpibusspeed;
return true;
}
// MacMan the following CPUs have fixed DMI2 speeds
case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm)
case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)
case CPU_MODEL_HASWELL_SVR: // Intel Core i7, Xeon E5 LGA2011v3
{
unsigned long dmi2speed;
dmi2speed = 5000;
DBG("dmi2speed %d\n", dmi2speed);
value->word = dmi2speed;
return true;
}
default:
break; //Unsupported CPU type
}
}
default:
break;
}
}
return false;
}
void setup_pci_devs(pci_dt_t *pci_dt)
{
char *devicepath;
bool doit, do_eth_devprop, do_wifi_devprop, /*do_usb_devprop,*/ do_gfx_devprop, do_enable_hpet, do_hda_devprop = false;
pci_dt_t *current = pci_dt;
getBoolForKey(kEthernetBuiltIn, &do_eth_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kEnableWifi, &do_wifi_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->chameleonConfig);
// getBoolForKey(kUsbInject, &do_usb_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kHDAEnabler, &do_hda_devprop, &bootInfo->chameleonConfig);
getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->chameleonConfig);
while (current)
{
devicepath = get_pci_dev_path(current);
switch (current->class_id)
{
case PCI_CLASS_BRIDGE_HOST:
//DBG("Setup BRIDGE_HOST \n");
if (current->dev.addr == PCIADDR(0, 0, 0))
{
dram_controller_dev = current;
}
break;
case PCI_CLASS_NETWORK_ETHERNET:
//DBG("Setup ETHERNET %s enabled\n", do_eth_devprop?"":"no");
if (do_eth_devprop)
{
setup_eth_builtin(current);
}
break;
case PCI_CLASS_NETWORK_OTHER:
//DBG("Setup WIRELESS %s enabled\n", do_wifi_devprop?"":"no");
if (do_wifi_devprop)
{
setup_wifi_airport(current);
}
break;
case PCI_CLASS_DISPLAY_VGA:
//DBG("GraphicsEnabler %s enabled\n", do_gfx_devprop?"":"no");
if (do_gfx_devprop)
{
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
if (getBoolForKey(kSkipAtiGfx, &doit, &bootInfo->chameleonConfig) && doit)
{
verbose("Skip ATi/AMD gfx device!\n");
}
else
{
setup_ati_devprop(current);
}
break;
case PCI_VENDOR_ID_INTEL:
if (getBoolForKey(kSkipIntelGfx, &doit, &bootInfo->chameleonConfig) && doit)
{
verbose("Skip Intel gfx device!\n");
}
else
{
setup_gma_devprop(current);
}
break;
case PCI_VENDOR_ID_NVIDIA:
if (getBoolForKey(kSkipNvidiaGfx, &doit, &bootInfo->chameleonConfig) && doit)
{
verbose("Skip Nvidia gfx device!\n");
}
else
{
setup_nvidia_devprop(current);
}
break;
}
}
break;
case PCI_CLASS_MULTIMEDIA_AUDIO_DEV:
//DBG("Setup HDEF %s enabled\n", do_hda_devprop?"":"no");
if (do_hda_devprop)
{
setup_hda_devprop(current);
}
break;
case PCI_CLASS_SERIAL_USB:
//DBG("USB fix \n");
notify_usb_dev(current);
/*if (do_usb_devprop)
{
set_usb_devprop(current);
}*/
break;
case PCI_CLASS_BRIDGE_ISA:
//DBG("Force HPET %s enabled\n", do_enable_hpet?"":"no");
if (do_enable_hpet)
{
force_enable_hpet(current);
}
break;
}
execute_hook("PCIDevice", current, NULL, NULL, NULL);
//DBG("setup_pci_devs current devID=%08x\n", current->device_id);
setup_pci_devs(current->children);
current = current->next;
}
}
