static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ u32 dword; u8 byte; ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif /* APU Internal Graphic Device*/ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); /* PCIe PortA */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); /* PCIe PortC */ PCI_INT(0x0, 0x15, 0x2, 0x12); /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; u32 dword; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ dword = 0; dword = pm_read8(0x34) & 0xF0; dword |= (pm_read8(0x35) & 0xFF) << 8; dword |= (pm_read8(0x36) & 0xFF) << 16; dword |= (pm_read8(0x37) & 0xFF) << 24; /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); apicid_hudson = IO_APIC_ID; smp_write_ioapic(mc, apicid_hudson, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } /* APIC IRQ routine */ for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); /* USB */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15); PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16); PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17); PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16); PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17); PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14); PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15); PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); /* FCH PCIe PortA */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* FCH PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); /* FCH PCIe PortC */ PCI_INT(0x0, 0x15, 0x2, 0x12); /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; u8 byte; dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 0)); if (dev) { dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sb700, 0x11, dword); /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= 0; /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); /* SATA */ dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif /* changes added to match acpi tables */ PCI_INT(0x0, 0x02, 0x0, 0x12); PCI_INT(0x0, 0x03, 0x0, 0x13); PCI_INT(0x0, 0x04, 0x0, 0x10); PCI_INT(0x0, 0x09, 0x0, 0x11); PCI_INT(0x0, 0x0A, 0x0, 0x12); PCI_INT(0x0, 0x12, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x3, 0x13); PCI_INT(0x0, 0x13, 0x2, 0x10); PCI_INT(0x0, 0x13, 0x2, 0x11); PCI_INT(0x0, 0x14, 0x1, 0x11); PCI_INT(0x0, 0x14, 0x3, 0x13); PCI_INT(0x1, 0x05, 0x2, 0x10); PCI_INT(0x1, 0x05, 0x3, 0x11); PCI_INT(0x2, 0x00, 0x0, 0x12); PCI_INT(0x2, 0x00, 0x1, 0x13); PCI_INT(0x2, 0x00, 0x2, 0x10); PCI_INT(0x2, 0x00, 0x3, 0x11); /* RS780 PCI to PCI bridge (PCIE port 4) */ PCI_INT(0x0, 0x09, 0x0, 0x11); /* usb */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ PCI_INT(0x0, 0x12, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x0, 0x12); PCI_INT(0x0, 0x13, 0x1, 0x13); PCI_INT(0x0, 0x14, 0x0, 0x10); /* sata */ PCI_INT(0x0, 0x11, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ PCI_INT(0x0, 0x14, 0x2, 0x12); /* on board NIC & Slot PCIE. */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */ PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */ /* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); */ /* Dev 2, external GFX */ /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ /* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */ /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); */ /* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */ PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */ /* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; int boot_apic_id; unsigned apic_version; unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; unsigned long cpu_flag; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); /*Inagua used dure core cpu with one die */ boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); cpu_features = result.eax; cpu_feature_flags = result.edx; cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; smp_write_processor(mc, 0, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); cpu_flag = MPC_CPU_ENABLED; smp_write_processor(mc, 1, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); get_bus_conf(); //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ device_t dev; u32 dword; u8 byte; dword = 0; dword = pm_ioread(0x34) & 0xF0; dword |= (pm_ioread(0x35) & 0xFF) << 8; dword |= (pm_ioread(0x36) & 0xFF) << 16; dword |= (pm_ioread(0x37) & 0xFF) << 24; /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); apicid_sb900 = IO_APIC_ID; smp_write_ioapic(mc, apicid_sb900, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } /* APIC IRQ routine */ for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); /* USB */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15); PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12); PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); /* FCH PCIe PortA */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* FCH PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); /* FCH PCIe PortC */ PCI_INT(0x0, 0x15, 0x2, 0x12); /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; device_t dev; u32 *dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); /* * AGESA v5 Apply apic enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ if (CONFIG_MAX_CPUS >= 16) apicid_sp5100 = 0x0; else apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0); smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); #ifdef UNUSED_CODE u8 byte; /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= 0; /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); /* SATA */ dword = (u32 *)pci_read_config32(dev, 0xAC); dword = dword & ~(7 << 26); dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); #endif /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin)) /* SMBUS */ //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 /* HD Audio */ PCI_INT(0x0, 0x14, 0x2, 0x10); /* USB */ /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ /* EHCI hard-wired to 02h, corresponding to using INTB# */ /* USB1 */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ /* USB2 */ PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG /* PCI slots */ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ PCI_INT(bus_pci, 0x5, 0x0, 0x14); PCI_INT(bus_pci, 0x5, 0x1, 0x15); PCI_INT(bus_pci, 0x5, 0x2, 0x16); PCI_INT(bus_pci, 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_pci, 0x6, 0x0, 0x15); PCI_INT(bus_pci, 0x6, 0x1, 0x16); PCI_INT(bus_pci, 0x6, 0x2, 0x17); PCI_INT(bus_pci, 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_pci, 0x7, 0x0, 0x16); PCI_INT(bus_pci, 0x7, 0x1, 0x17); PCI_INT(bus_pci, 0x7, 0x2, 0x14); PCI_INT(bus_pci, 0x7, 0x3, 0x15); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; u32 dword; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ dword = 0; dword = pm_ioread(0x34) & 0xF0; dword |= (pm_ioread(0x35) & 0xFF) << 8; dword |= (pm_ioread(0x36) & 0xFF) << 16; dword |= (pm_ioread(0x37) & 0xFF) << 24; smp_write_ioapic(mc, apicid_sb800, 0x11, dword); for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); */ PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; u32 apicid_sb700; u32 apicid_rd890; device_t dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); /* * AGESA v5 Apply apic enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ if (CONFIG_MAX_CPUS >= 16) apicid_sb700 = 0x0; else apicid_sb700 = CONFIG_MAX_CPUS + 1; apicid_rd890 = apicid_sb700 + 1; //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); if (dev) { /* Set sb700 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sb700, 0x20, dword); /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; smp_write_ioapic(mc, apicid_rd890, 0x20, dword); } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) /* SMBUS */ //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 /* HD Audio */ PCI_INT(0x0, 0x14, 0x2, 0x10); /* USB */ /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ /* EHCI hard-wired to 02h, corresponding to using INTB# */ /* USB1 */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ /* USB2 */ PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG /* on board NIC & Slot PCIE. */ /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13); */ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600); mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ { device_t dev; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { struct resource *res; res = find_resource(dev, 0x74); smp_write_ioapic(mc, apicid_sb600, 0x20, res2mmio(res, 0, 0)); } } mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) /* usb */ PCI_INT(0x0, 0x13, 0x0, 0x10); PCI_INT(0x0, 0x13, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x2, 0x12); PCI_INT(0x0, 0x13, 0x3, 0x13); /* sata */ PCI_INT(0x0, 0x12, 0x1, 0x16); /* SMBus/ACPI */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* IDE */ PCI_INT(0x0, 0x14, 0x1, 0x11); /* HDA */ PCI_INT(0x0, 0x14, 0x2, 0x12); /* LPC */ PCI_INT(0x0, 0x14, 0x3, 0x13); /* GFX ? */ PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); /* PCIe slots */ PCI_INT(0x2, 0x00, 0x00, 0x10); PCI_INT(0x2, 0x00, 0x01, 0x11); PCI_INT(0x2, 0x00, 0x02, 0x12); PCI_INT(0x2, 0x00, 0x03, 0x13); /* PCIe slots */ PCI_INT(0x3, 0x00, 0x00, 0x11); PCI_INT(0x3, 0x00, 0x01, 0x12); PCI_INT(0x3, 0x00, 0x02, 0x13); PCI_INT(0x3, 0x00, 0x03, 0x10); /* PCIe slots */ PCI_INT(0x4, 0x00, 0x00, 0x12); PCI_INT(0x4, 0x00, 0x01, 0x13); PCI_INT(0x4, 0x00, 0x02, 0x10); PCI_INT(0x4, 0x00, 0x03, 0x11); /* PCIe slots */ PCI_INT(0x5, 0x00, 0x00, 0x13); PCI_INT(0x5, 0x00, 0x01, 0x10); PCI_INT(0x5, 0x00, 0x02, 0x11); PCI_INT(0x5, 0x00, 0x03, 0x12); /* onboard NIC ? */ PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13); PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10); PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; unsigned sbdn; get_bus_conf(); sbdn = sysconf.sbdn; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; u32 dword; dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); } /* Initialize interrupt mapping */ /* copied from stock bios */ /*0x01800500,0x1800d509,0x00520d08*/ dword = 0x08d0d218; pci_write_config32(dev, 0x7c, dword); dword = 0x8d001509; pci_write_config32(dev, 0x80, dword); dword = 0x00010271; pci_write_config32(dev, 0x84, dword); } } /* Now, assemble the table. */ mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin)) #if 0 // Onboard ck804 smbus PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */ #endif // Onboard ck804 USB PCI_INT(0, sbdn+2, 0, 23); PCI_INT(0, sbdn+2, 1, 23); // Onboard ck804 AC-97 PCI_INT(0, sbdn+4, 0, 23); // Onboard ck804 SATA 0 PCI_INT(0, sbdn+7, 0, 20); // Onboard ck804 SATA 1 PCI_INT(0, sbdn+8, 0, 21); // Onboard ck804 NIC PCI_INT(0, sbdn+10, 0, 22); /* "AGR" slot */ PCI_INT(1, 0, 0, 16); PCI_INT(1, 0, 1, 17); /* legacy PCI */ PCI_INT(1, 7, 0, 17); PCI_INT(1, 7, 1, 18); PCI_INT(1, 7, 2, 19); PCI_INT(1, 7, 3, 16); PCI_INT(1, 8, 0, 18); PCI_INT(1, 8, 1, 19); PCI_INT(1, 8, 2, 16); PCI_INT(1, 8, 3, 17); PCI_INT(1, 9, 0, 19); PCI_INT(1, 9, 1, 16); PCI_INT(1, 9, 2, 17); PCI_INT(1, 9, 3, 18); /* PCI-E x1 port */ PCI_INT(2, 0, 0, 19); /* XXX guesses */ PCI_INT(2, 0, 1, 16); PCI_INT(2, 0, 2, 17); PCI_INT(2, 0, 3, 18); /* PCI-E x16 port */ /* XXX fix me ? */ PCI_INT(3, 0, 0, 18); /* XXX guesses */ PCI_INT(3, 0, 1, 19); PCI_INT(3, 0, 2, 16); PCI_INT(3, 0, 3, 17); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_ck804[0]); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "PA78VM5 "; struct mp_config_table *mc; int j; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); get_bus_conf(); /* Bus: Bus ID Type */ /* define bus and isa numbers */ for (j = 0; j < bus_isa; j++) { smp_write_bus(mc, j, (char *)"PCI "); } smp_write_bus(mc, bus_isa, (char *)"ISA "); /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; u8 byte; dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 0)); if (dev) { dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sb700, 0x11, dword); /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= 0; /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); /* SATA */ dword = pci_read_config32(dev, 0xac); dword &= ~(7 << 26); dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif /* usb */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ PCI_INT(0x0, 0x12, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x0, 0x12); PCI_INT(0x0, 0x13, 0x1, 0x13); PCI_INT(0x0, 0x14, 0x0, 0x10); /* sata */ PCI_INT(0x0, 0x11, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ /* on board NIC & Slot PCIE. */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); */ PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_sis966, 0x11, res2mmio(res, 0, 0)); } dword = 0x43c6c643; pci_write_config32(dev, 0x7c, dword); dword = 0x81001a00; pci_write_config32(dev, 0x80, dword); dword = 0xd0001202; pci_write_config32(dev, 0x84, dword); } } mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin)) PCI_INT(0, sbdn+1, 1, 0xa); PCI_INT(0, sbdn+2, 0, 0x16); // 22 PCI_INT(0, sbdn+2, 1, 0x17); // 23 PCI_INT(0, sbdn+6, 1, 0x17); // 23 PCI_INT(0, sbdn+5, 0, 0x14); // 20 PCI_INT(0, sbdn+5, 1, 0x17); // 23 PCI_INT(0, sbdn+5, 2, 0x15); // 21 PCI_INT(0, sbdn+8, 0, 0x16); // 22 for(j=7; j>=2; j--) { if(!bus_sis966[j]) continue; for(i=0; i<4; i++) { PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j=0; j<2; j++) for(i=0; i<4; i++) { PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); /* Now, assemble the table. */ mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin)) // PCI slot 1 PCI_INT(0, 8, 0, 16); PCI_INT(0, 8, 1, 17); PCI_INT(0, 8, 2, 18); PCI_INT(0, 8, 3, 19); // PCI slot 2 PCI_INT(0, 9, 0, 17); PCI_INT(0, 9, 1, 18); PCI_INT(0, 9, 2, 19); PCI_INT(0, 9, 3, 16); // SATA PCI_INT(0, 15, 1, 20); // USB PCI_INT(0, 16, 0, 21); PCI_INT(0, 16, 1, 21); PCI_INT(0, 16, 2, 21); PCI_INT(0, 16, 3, 21); // Audio PCI_INT(0, 17, 2, 22); // Ethernet PCI_INT(0, 18, 0, 23); /* Onboard VGA */ PCI_INT(1, 0, 0, 16); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, 0); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; struct device *dev; uint8_t sp5100_bus_number; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) apicid_sp5100 = 0x0; else apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { uint32_t *dword_ptr; uint32_t dword; uint16_t word; uint8_t byte; sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0)); if (dev) { dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr); /* Initialize interrupt mapping */ /* USB 1 & 2 */ word = pci_read_config16(dev, 0xbe); word &= ~0x3f3f; word |= 0x0; /* 0: INTA, ...., 7: INTH */ word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */ word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */ word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */ pci_write_config16(dev, 0xbe, word); /* USB 3 */ byte = pci_read_config8(dev, 0x63); byte &= 0xf8; byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */ pci_write_config8(dev, 0x63, byte); dword = pci_read_config32(dev, 0xac); /* SATA */ dword &= ~(7 << 26); dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */ /* Hide IDE */ dword &= ~(0x00080000); /* dword_ptr |= 1 << 22; PIC and APIC co exists */ pci_write_config32(dev, 0xac, dword); /* * 00:12.0: PROG SATA : INT F * 00:13.0: INTA USB_0 * 00:13.1: INTB USB_1 * 00:13.2: INTC USB_2 * 00:13.3: INTD USB_3 * 00:13.4: INTC USB_4 * 00:13.5: INTD USB2 * 00:14.1: INTA IDE * 00:14.2: Prog HDA : INT E * 00:14.5: INTB ACI * 00:14.6: INTB MCI */ } dev = pcidev_on_root(0, 0); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr); } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); /* SR5650 devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ dev = pcidev_on_root(0x2, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */ } dev = pcidev_on_root(0x4, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */ } dev = pcidev_on_root(0x9, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */ } dev = pcidev_on_root(0xa, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */ } dev = pcidev_on_root(0xb, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */ } dev = pcidev_on_root(0xc, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ } dev = pcidev_on_root(0xd, 0); if (dev && dev->enabled) { uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ } /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, interrupt_signal, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin)) /* USB1 */ PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */ /* USB2 */ PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */ PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */ /* USB3 */ PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */ /* SATA */ PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */ /* PCI slots */ dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ PCI_INT(bus_pci, 0x1, 0x0, 0x15); PCI_INT(bus_pci, 0x1, 0x1, 0x16); PCI_INT(bus_pci, 0x1, 0x2, 0x17); PCI_INT(bus_pci, 0x1, 0x3, 0x14); /* PCI_SLOT 1. */ PCI_INT(bus_pci, 0x2, 0x0, 0x14); PCI_INT(bus_pci, 0x2, 0x1, 0x15); PCI_INT(bus_pci, 0x2, 0x2, 0x16); PCI_INT(bus_pci, 0x2, 0x3, 0x17); /* PCI_SLOT 2. */ PCI_INT(bus_pci, 0x3, 0x0, 0x16); PCI_INT(bus_pci, 0x3, 0x1, 0x17); PCI_INT(bus_pci, 0x3, 0x2, 0x14); PCI_INT(bus_pci, 0x3, 0x3, 0x15); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned int sbdn; int i, j, bus_isa; device_t dev; struct resource *res; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); pci_write_config32(dev, 0x7c, 0x00000000); pci_write_config32(dev, 0x80, 0x11002009); pci_write_config32(dev, 0x84, 0x2000dd08); } mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0); /* I/O Ints */ PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */ PCI_INT(0, sbdn + 2, 0, 20); /* USB 1.1 */ PCI_INT(0, sbdn + 2, 1, 22); /* USB 2.0 */ PCI_INT(0, sbdn + 4, 0, 14); /* IDE */ PCI_INT(0, sbdn + 5, 0, 23); /* SATA 0 */ PCI_INT(0, sbdn + 5, 1, 23); /* SATA 1 */ PCI_INT(0, sbdn + 5, 2, 22); /* SATA 2 */ PCI_INT(0, sbdn + 6, 1, 21); /* HD audio */ PCI_INT(0, sbdn + 8, 0, 24); /* NIC */ /* PCI-E slots (two x1, one x4, one x16) */ for (j = 7; j >= 2; j--) { if (!bus_mcp55[j]) continue; for (i = 0; i < 4; i++) PCI_INT(j, 0, i, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4); } /* PCI slots (three on this board) */ for (j = 0; j < 3; j++) { for (i = 0; i < 4; i++) PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4); } /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa); /* Compute the checksums. */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; static const char productid[12] = "PC2500 "; struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); /* Now, assemble the table. */ mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin)) // PCI slot 1 PCI_INT(0, 8, 0, 16); PCI_INT(0, 8, 1, 17); PCI_INT(0, 8, 2, 18); PCI_INT(0, 8, 3, 19); // PCI slot 2 PCI_INT(0, 9, 0, 17); PCI_INT(0, 9, 1, 18); PCI_INT(0, 9, 2, 19); PCI_INT(0, 9, 3, 16); // SATA PCI_INT(0, 15, 1, 20); // USB PCI_INT(0, 16, 0, 21); PCI_INT(0, 16, 1, 21); PCI_INT(0, 16, 2, 21); PCI_INT(0, 16, 3, 21); // Audio PCI_INT(0, 17, 2, 22); // Ethernet PCI_INT(0, 18, 0, 23); /* Onboard VGA */ PCI_INT(1, 0, 0, 16); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0, 0x0, MP_APIC_ALL, 0x0); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); }