/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
PHY_RF6052SetBandwidth8192E(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth) //20M or 40M
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch(Bandwidth)
{
case CHANNEL_WIDTH_20:
//RT_DISP(FIOCTL, IOCTL_STATE, ("PHY_RF6052SetBandwidth8192E(), set 20MHz, pHalData->RfRegChnlVal[0] = 0x%x \n", pHalData->RfRegChnlVal[0]));
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11 );
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case CHANNEL_WIDTH_40:
//RT_DISP(FIOCTL, IOCTL_STATE, ("PHY_RF6052SetBandwidth8192E(), set 40MHz, pHalData->RfRegChnlVal[0] = 0x%x \n", pHalData->RfRegChnlVal[0]));
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 );
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_RF6052SetBandwidth8192E(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
for(eRFPath=0;eRFPath<pHalData->NumTotalRFPath;eRFPath++)
{
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffff3ff) | 0x0400);
PHY_SetRFReg(Adapter, eRFPath, RF_CHNLBW, 0xff, pHalData->RfRegChnlVal[eRFPath]);
}
break;
case HT_CHANNEL_WIDTH_40:
for(eRFPath=0;eRFPath<pHalData->NumTotalRFPath;eRFPath++)
{
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffff3ff));
PHY_SetRFReg(Adapter, eRFPath, RF_CHNLBW, 0xcff, pHalData->RfRegChnlVal[eRFPath]);
}
break;
default:
//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: struct adapter * Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void PHY_RF6052SetBandwidth8723B(
struct adapter *Adapter, enum CHANNEL_WIDTH Bandwidth
) /* 20M or 40M */
{
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) {
case CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11);
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
PHY_SetRFReg(Adapter, ODM_RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10);
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
PHY_SetRFReg(Adapter, ODM_RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth)); */
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
rtl8188e_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
}
void
ODM_SetRFReg(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
#endif
}
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
#endif
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: struct adapter *Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
enum ht_channel_width Bandwidth)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
break;
}
}
void DMDP_PHY_SetRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath, unsigned int RegAddr,
unsigned int BitMask, unsigned int Data)
{
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return;
}
PHY_SetRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, Data);
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWMode23aCallback8190Pci() only
*
* Input: struct rtw_adapter * Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void rtl8723a_phy_rf6052set_bw(
struct rtw_adapter *Adapter,
enum ht_channel_width Bandwidth) /* 20M or 40M */
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
PHY_RF6052SetBandwidth8812(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth) //20M or 40M
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch(Bandwidth)
{
case CHANNEL_WIDTH_20:
//DBG_871X("PHY_RF6052SetBandwidth8812(), set 20MHz\n");
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
break;
case CHANNEL_WIDTH_40:
//DBG_871X("PHY_RF6052SetBandwidth8812(), set 40MHz\n");
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
break;
case CHANNEL_WIDTH_80:
//DBG_871X("PHY_RF6052SetBandwidth8812(), set 80MHz\n");
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
break;
default:
DBG_871X("PHY_RF6052SetBandwidth8812(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
/*-----------------------------------------------------------------------------
* Function: RF_ChangeTxPath
*
* Overview: For RL6052, we must change some RF settign for 1T or 2T.
*
* Input: u2Byte DataRate // 0x80-8f, 0x90-9f
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 09/25/2008 MHC Create Version 0.
* Firmwaer support the utility later.
*
*---------------------------------------------------------------------------*/
void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
#if 0//(RTL92SE_FPGA_VERIFY == 0)
static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
// Set PA to high value
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
// Set PA low gain
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
}
#endif
} /* RF_ChangeTxPath */
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
rtl8192d_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
//RT_TRACE(COMP_MLME,DBG_LOUD,("====>PHY_RF6052SetBandwidth()Bandwidth:%d \n",Bandwidth));
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
for(eRFPath=0;eRFPath<pHalData->NumTotalRFPath;eRFPath++)
{
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffff3ff) | 0x0400);
//PHY_SetRFReg(Adapter, eRFPath, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, RF_CHNLBW, BIT10|BIT11, 0x01);
//RT_TRACE(COMP_RF, DBG_LOUD, ("PHY_RF6052SetBandwidth 20M RF 0x18 = 0x%x interface index %d\n",pHalData->RfRegChnlVal[eRFPath], Adapter->interfaceIndex));
}
break;
case HT_CHANNEL_WIDTH_40:
for(eRFPath=0;eRFPath<pHalData->NumTotalRFPath;eRFPath++)
{
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffff3ff));
//PHY_SetRFReg(Adapter, eRFPath, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, RF_CHNLBW, BIT10|BIT11, 0x00);
//RT_TRACE(COMP_RF, DBG_LOUD, ("PHY_RF6052SetBandwidth 40M RF 0x18 = 0x%x interface index %d\n",pHalData->RfRegChnlVal[eRFPath], Adapter->interfaceIndex));
}
break;
default:
//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
//RT_TRACE(COMP_MLME,DBG_LOUD,("<==== PHY_RF6052SetBandwidth()Bandwidth:%d \n",Bandwidth));
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void
PHY_RF6052SetBandwidth(
struct net_device* dev,
HT_CHANNEL_WIDTH Bandwidth)
{
struct r8192_priv *priv = rtllib_priv(dev);
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
PHY_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_20_40:
priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff));
PHY_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
break;
}
}
/*------------------------Define function prototype--------------------------*/
extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate)
{
#if 0
static u1Byte RF_Path_Type = 2;
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x0f000);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G3, bMask20Bits, 0xeacf1);
for (i = 0; i < 6; i++)
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x04440);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G3, bMask20Bits, 0xea4f1);
for (i = 0; i < 6; i++)
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x01e19);
}
#endif
} /* RF_ChangeTxPath */
extern void
PHY_RFShadowRecorver(
struct net_device* dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset)
{
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
{
if (RF_Shadow[eRFPath][Offset].Recorver == true)
{
PHY_SetRFReg( dev, eRFPath, Offset, bRFRegOffsetMask,
RF_Shadow[eRFPath][Offset].Value);
RT_TRACE(COMP_INIT,
"PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
}
}
} /* PHY_RFShadowRecorver */
VOID
PHY_RFShadowRecorver(
IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 Offset)
{
// Check if the address is error
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE)
{
// Check if we need to recorver the register.
if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE)
{
PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
RF_Shadow[eRFPath][Offset].Value);
//RT_TRACE(COMP_INIT, DBG_LOUD,
//("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
//eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
}
}
} /* PHY_RFShadowRecorver */
void rtw_bb_rf_gain_offset(struct adapter *padapter)
{
u8 value = padapter->eeprompriv.EEPROMRFGainOffset;
u32 res, i = 0;
u32 *Array = Array_kfreemap;
u32 v1 = 0, v2 = 0, target = 0;
/* DBG_871X("+%s value: 0x%02x+\n", __func__, value); */
if (value & BIT4) {
DBG_871X("Offset RF Gain.\n");
DBG_871X("Offset RF Gain. padapter->eeprompriv.EEPROMRFGainVal = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal);
if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
res &= 0xfff87fff;
DBG_871X("Offset RF Gain. before reg 0x7f = 0x%08x\n", res);
/* res &= 0xfff87fff; */
for (i = 0; i < ARRAY_SIZE(Array_kfreemap); i += 2) {
v1 = Array[i];
v2 = Array[i+1];
if (v1 == padapter->eeprompriv.EEPROMRFGainVal) {
DBG_871X("Offset RF Gain. got v1 = 0x%x , v2 = 0x%x\n", v1, v2);
target = v2;
break;
}
}
DBG_871X("padapter->eeprompriv.EEPROMRFGainVal = 0x%x , Gain offset Target Value = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal, target);
PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
/* res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; */
/* rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); */
res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
DBG_871X("Offset RF Gain. After reg 0x7f = 0x%08x\n", res);
} else
DBG_871X("Offset RF Gain. padapter->eeprompriv.EEPROMRFGainVal = 0x%x != 0xff, didn't run Kfree\n", padapter->eeprompriv.EEPROMRFGainVal);
} else
DBG_871X("Using the default RF gain.\n");
}
void
odm_ConfigRFReg_8723B(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
if (Addr == 0xfe || Addr == 0xffe)
{
msleep(50);
}
else
{
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
/* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
if (Addr == 0xb6)
{
u4Byte getvalue = 0;
u1Byte count = 0;
getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
udelay(1);
while ((getvalue>>8)!=(Data>>8))
{
count++;
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
udelay(1);
getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data, count));
if (count>5)
break;
}
}
if (Addr == 0xb2)
{
u4Byte getvalue = 0;
u1Byte count = 0;
getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
udelay(1);
while (getvalue!=Data)
{
count++;
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
udelay(1);
/* Do LCK againg */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
udelay(1);
getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data, count));
if (count>5)
break;
}
}
}
static int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue=0;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 *pszRadioAFile = NULL, *pszRadioBFile = NULL;
static s8 sz92DRadioAFile[] = RTL8192D_PHY_RADIO_A;
static s8 sz92DRadioBFile[] = RTL8192D_PHY_RADIO_B;
static s8 sz92DRadioAintPAFile[] = RTL8192D_PHY_RADIO_A_intPA;
static s8 sz92DRadioBintPAFile[] = RTL8192D_PHY_RADIO_B_intPA;
BOOLEAN bMac1NeedInitRadioAFirst = _FALSE,bMac0NeedInitRadioBFirst = _FALSE;
BOOLEAN bNeedPowerDownRadioA = _FALSE,bNeedPowerDownRadioB = _FALSE;
BOOLEAN bTrueBPath = _FALSE;//vivi added this for read parameter from header, 20100908
u32 MaskforPhySet = 0; //For 92d PHY cross access, 88c must set value 0.
pszRadioAFile = sz92DRadioAFile;
pszRadioBFile = sz92DRadioBFile;
if(pHalData->InternalPA5G[0])
pszRadioAFile = sz92DRadioAintPAFile;
if(pHalData->InternalPA5G[1])
pszRadioBFile = sz92DRadioBintPAFile;
//DMDP,MAC0 on G band,MAC1 on A band.
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
{
if(pHalData->CurrentBandType92D == BAND_ON_2_4G && pHalData->interfaceIndex == 0)
{
//MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write.
if(rtl8192d_PHY_EnableAnotherPHY(Adapter, _TRUE))
{
pHalData->NumTotalRFPath = 2;
bMac0NeedInitRadioBFirst = _TRUE;
}
else
{
// We think if MAC1 is ON,then radio_a.txt and radio_b.txt has been load.
return rtStatus;
}
}
else if(pHalData->CurrentBandType92D == BAND_ON_5G && pHalData->interfaceIndex == 1)
{
//MAC1 Need PHY0 load radio_a.txt . Driver use DBI to write.
if(rtl8192d_PHY_EnableAnotherPHY(Adapter, _FALSE))
{
pHalData->NumTotalRFPath = 2;
bMac1NeedInitRadioAFirst = _TRUE;
}
else
{
// We think if MAC0 is ON,then radio_a.txt and radio_b.txt has been load.
return rtStatus;
}
}
else if(pHalData->interfaceIndex == 1)
{
// MAC0 enabled, only init radia B.
pszRadioAFile = pszRadioBFile;
bTrueBPath = _TRUE; //vivi added this for read parameter from header, 20100909
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_RF6052_Config_ParaFile() Radio_A:%s\n",pszRadioAFile));
//RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_RF6052_Config_ParaFile() Radio_B:%s\n",pszRadioBFile));
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
if (bMac1NeedInitRadioAFirst) //Mac1 use PHY0 write
{
if (eRFPath == RF_PATH_A)
{
bNeedPowerDownRadioA = _TRUE;
MaskforPhySet = MAC1_ACCESS_PHY0;
}
else if (eRFPath == RF_PATH_B)
{
MaskforPhySet = 0;
bMac1NeedInitRadioAFirst = _FALSE;
eRFPath = RF_PATH_A;
bTrueBPath = _TRUE;
pszRadioAFile = pszRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
else if (bMac0NeedInitRadioBFirst) //Mac0 use PHY1 write
{
if (eRFPath == RF_PATH_A)
{
MaskforPhySet = 0;
}
if (eRFPath == RF_PATH_B)
{
MaskforPhySet = MAC0_ACCESS_PHY1;
bMac0NeedInitRadioBFirst = _FALSE;
bNeedPowerDownRadioB = _TRUE;
eRFPath = RF_PATH_A;
bTrueBPath = _TRUE;
pszRadioAFile = pszRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV);
break;
case RF_PATH_B :
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe|MaskforPhySet, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo|MaskforPhySet, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
//vivi added this for read parameter from header, 20100908
if(bTrueBPath == _TRUE)
rtStatus = rtl8192d_PHY_ConfigRFWithHeaderFile(Adapter,radiob_txt|MaskforPhySet, (RF_RADIO_PATH_E)eRFPath);
else
rtStatus = rtl8192d_PHY_ConfigRFWithHeaderFile(Adapter,radioa_txt|MaskforPhySet, (RF_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192d_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
#endif
break;
case RF_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus = rtl8192d_PHY_ConfigRFWithHeaderFile(Adapter,radiob_txt, (RF_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192d_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
#endif
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B :
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
if (bNeedPowerDownRadioA)
{
// check MAC0 enable or not again now, if enabled, not power down radio A.
rtl8192d_PHY_PowerDownAnotherPHY(Adapter, _FALSE);
}
else if (bNeedPowerDownRadioB)
{
// check MAC1 enable or not again now, if enabled, not power down radio B.
rtl8192d_PHY_PowerDownAnotherPHY(Adapter, _TRUE);
}
for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
#if MP_DRIVER == 1
PHY_SetRFReg(Adapter, eRFPath, RF_RXRF_A3, bRFRegOffsetMask, 0xff456);
#endif
pdmpriv->RegRF3C[eRFPath] = PHY_QueryRFReg(Adapter, eRFPath, RF_RXRF_A3, bRFRegOffsetMask);
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
PHY_RF6052SetBandwidth8188F(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth) /*20M or 40M */
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) {
case CHANNEL_WIDTH_20:
/*
RF_A_reg 0x18[11:10]=2'b11
RF_A_reg 0x87=0x00065
RF_A_reg 0x1c=0x00000
RF_A_reg 0x52=0xFAC2C (for USB)
RF_A_reg 0xDF=0x00140
RF_A_reg 0x1b=0x00c6c
*/
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11);
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); /* RF TRX_BW */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x87, bRFRegOffsetMask, 0x00065); /* FILTER BW&RC Corner (ACPR) */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1C, bRFRegOffsetMask, 0x00000); /* FILTER BW&RC Corner (ACPR) */
#ifdef CONFIG_USB_HCI
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x52, bRFRegOffsetMask, 0xFAC2C); /* FILTER BW&RC Corner (ACPR) */
#endif /* CONFIG_USB_HCI */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0xDF, bRFRegOffsetMask, 0x00140); /* FILTER BW&RC Corner (ACPR) */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1B, bRFRegOffsetMask, 0x00C6C); /* FILTER BW&RC Corner (ACPR) */
break;
case CHANNEL_WIDTH_40:
/*
RF_A_reg 0x18[11:10]=2'b01
RF_A_reg 0x87=0x00025
RF_A_reg 0x1c=0x00800 (for SDIO)
RF_A_reg 0x1c=0x01000 (for USB)
RF_A_reg 0x52=0xFAC2C (for USB)
RF_A_reg 0xDF=0x00140
RF_A_reg 0x1b=0x00c6c
*/
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10);
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); /* RF TRX_BW */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x87, bRFRegOffsetMask, 0x00025); /* FILTER BW&RC Corner (ACPR) */
#ifdef CONFIG_SDIO_HCI
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1C, bRFRegOffsetMask, 0x00800); /* FILTER BW&RC Corner (ACPR) */
#endif /* CONFIG_SDIO_HCI */
#ifdef CONFIG_USB_HCI
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1C, bRFRegOffsetMask, 0x01000); /* FILTER BW&RC Corner (ACPR) */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x52, bRFRegOffsetMask, 0xFAC2C); /* FILTER BW&RC Corner (ACPR) */
#endif
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0xDF, bRFRegOffsetMask, 0x00140); /* FILTER BW&RC Corner (ACPR) */
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1B, bRFRegOffsetMask, 0x00C6C); /* FILTER BW&RC Corner (ACPR) */
break;
default:
/*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
break;
}
}
void mptbt_open_WiFiRF(PADAPTER Adapter)
{
PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3);
PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2);
PHY_SetRFReg(Adapter, RF90_PATH_A, 0x0, 0xF0000, 0x3);
}
