static void configPIO(void) { /* Setup PIO of ASC device */ SET_PIO_ASC(PIO_PORT(4), 3, 2, 4, 5); /* Setup up ethernet reset */ SET_PIO_PIN(PIO_PORT(2), 6, STPIO_OUT); }
int board_init(void) { unsigned long sysconf; /* Route UART2 instead of SCI to PIO4 */ /* Set ssc2_mux_sel = 0 */ sysconf = *STB7100_SYSCONF_SYS_CFG07; sysconf &= ~(1<<3); *STB7100_SYSCONF_SYS_CFG07 = sysconf; configPIO(); #ifdef CONFIG_DRIVER_SMC91111 /* Reset ethernet chip */ STPIO_SET_PIN(PIO_PORT(2), 6, 0); udelay(1000); STPIO_SET_PIN(PIO_PORT(2), 6, 1); udelay(1000); STPIO_SET_PIN(PIO_PORT(2), 6, 0); #endif #if defined(CONFIG_CMD_IDE) #ifdef CONFIG_SH_STB7100_IDE stb7100ref_init_ide(); #endif #ifdef CONFIG_SH_STB7100_SATA stb7100_sata_init(); #endif #endif return 0; }
static void configSerial (void) { unsigned long sysconf; #if (CONFIG_SYS_STM_ASC_BASE == CONFIG_SYS_STM_ASC2_BASE) /* Setup PIO of ASC device */ SET_PIO_ASC(PIO_PORT(1), 2, 3, 5, 4); /* UART2 - AS0 */ /* Route UART2 via PIO1 for TX, RX, CTS & RTS */ sysconf = *STX5197_HD_CONF_MON_CONFIG_CONTROL_F; ALTFOP(sysconf,1,2,1); /* PIO1[2] AltFunction = 1 */ ALTFOP(sysconf,1,3,1); /* PIO1[3] AltFunction = 1 */ ALTFOP(sysconf,1,4,1); /* PIO1[4] AltFunction = 1 */ ALTFOP(sysconf,1,5,1); /* PIO1[5] AltFunction = 1 */ *STX5197_HD_CONF_MON_CONFIG_CONTROL_F = sysconf; #elif (CONFIG_SYS_STM_ASC_BASE == CONFIG_SYS_STM_ASC3_BASE) /* Setup PIO of ASC device */ SET_PIO_ASC(PIO_PORT(2), 0, 1, 2, 5); /* UART3 - AS1 */ /* Route UART3 via PIO2 for TX, RX, CTS & RTS */ sysconf = *STX5197_HD_CONF_MON_CONFIG_CONTROL_G; ALTFOP(sysconf,2,0,1); /* PIO2[0] AltFunction = 1 */ ALTFOP(sysconf,2,1,1); /* PIO2[1] AltFunction = 1 */ ALTFOP(sysconf,2,2,1); /* PIO2[2] AltFunction = 1 */ ALTFOP(sysconf,2,5,1); /* PIO2[5] AltFunction = 1 */ *STX5197_HD_CONF_MON_CONFIG_CONTROL_G = sysconf; #else #error Unknown serial port configuration! #endif }
extern int stx7105_usb_init(int port, int over_current, int power_ctrl) { unsigned long reg; const unsigned char oc_pins[2] = {4, 6}; /* PIO4 */ const unsigned char power_pins[2] = {5, 7}; /* PIO4 */ if (port >= sizeof(oc_pins)) /* invalid port number ? */ return -1; /* failed to initialize! */ /* Power on the USB */ reg = readl(STX7105_SYSCONF_SYS_CFG32); /* Power up USB host controller */ /* USBn_HC_POWER_DOWN_REQ = 0 = Powered Up */ reg &= ~(1ul<<(4+port)); /* Power up USB PHY */ /* USBn_PHY_POWER_DOWN_REQ = 0 = Powered Up */ reg &= ~(1ul<<(6+port)); writel(reg, STX7105_SYSCONF_SYS_CFG32); if (over_current) { /* USB overcurrent enable */ reg = readl(STX7105_SYSCONF_SYS_CFG04); /* USB0_PRT_OVCURR_POL = 0 = Active Low */ reg &= ~(1ul<<(3+port)); /* USBn_PRT_OVCURR_IN = 0 = PIO4[oc_pins[port]] */ reg &= ~(1ul<<(5+port)); /* CFG_USBn_OVRCURR_ENABLE = 1 = OC Enabled */ reg |= 1ul<<(11+port); writel(reg, STX7105_SYSCONF_SYS_CFG04); /* Route USBn OC Routing via PIO4[oc_pins[port]] */ reg = readl(STX7105_SYSCONF_SYS_CFG34); /* PIO4[oc_pins[port]] CFG34[8+oc_pins[port],oc_pins[port]] = Alternate4 */ reg &= ~(0x0101ul<<(oc_pins[port])); /* Mask=3 */ reg |= 0x0101ul<<(oc_pins[port]); /* OR=3 */ writel(reg, STX7105_SYSCONF_SYS_CFG34); /* set PIO directionality, for OC as IN */ SET_PIO_PIN(PIO_PORT(4), oc_pins[port], STPIO_IN); } if (power_ctrl) { /* Route USBn POWER Routing via PIO4[power_pins[port]] */ reg = readl(STX7105_SYSCONF_SYS_CFG34); /* PIO4[power_pins[port]] CFG34[8+power_pins[port],power_pins[port]] = Alternate4 */ reg &= ~(0x0101ul<<(power_pins[port])); /* Mask=3 */ reg |= 0x0101ul<<(power_pins[port]); /* OR=3 */ writel(reg, STX7105_SYSCONF_SYS_CFG34); /* set PIO directionality, for POWER as ALT_OUT */ SET_PIO_PIN(PIO_PORT(4), power_pins[port], STPIO_ALT_OUT); } /* start the USB Wrapper Host Controller */ ST40_start_host_control( USB_FLAGS_STRAP_8BIT | USB_FLAGS_STBUS_CONFIG_THRESHOLD128); return 0; }
extern void stx7141_usb_init(void) { #ifdef QQQ /* QQQ - TO DO */ unsigned long reg, req_reg; /* Power on the USB */ reg = readl(STX7141_SYSCONF_SYS_CFG32); reg &= ~(1ul<<4); /* USB_POWER_DOWN_REQ = 0 */ writel(reg, STX7141_SYSCONF_SYS_CFG32); /* Work around for USB over-current detection chip being * active low, and the 7141 being active high. * Note this is an undocumented bit, which apparently enables * an inverter on the overcurrent signal. */ reg = readl(STX7141_SYSCONF_SYS_CFG06); reg |= 1ul<<29; writel(reg, STX7141_SYSCONF_SYS_CFG06); /* USB oc */ SET_PIO_PIN(PIO_PORT(5), 6, STPIO_IN); /* USB power */ SET_PIO_PIN(PIO_PORT(5), 7, STPIO_ALT_OUT); STPIO_SET_PIN(PIO_PORT(5), 7, 1); /* Set strap mode */ #define STRAP_MODE AHB2STBUS_STRAP_16_BIT reg = readl(AHB2STBUS_STRAP); #if STRAP_MODE == 0 reg &= ~AHB2STBUS_STRAP_16_BIT; #else reg |= STRAP_MODE; #endif writel(reg, AHB2STBUS_STRAP); /* Start PLL */ reg = readl(AHB2STBUS_STRAP); writel(reg | AHB2STBUS_STRAP_PLL, AHB2STBUS_STRAP); udelay(100000); /* QQQ: can this delay be shorter ? */ writel(reg & (~AHB2STBUS_STRAP_PLL), AHB2STBUS_STRAP); udelay(100000); /* QQQ: can this delay be shorter ? */ req_reg = (1<<21) | /* Turn on read-ahead */ (5<<16) | /* Opcode is store/load 32 */ (0<<15) | /* Turn off write posting */ (1<<14) | /* Enable threshold */ (3<<9) | /* 2**3 Packets in a chunk */ (0<<4) | /* No messages */ (8<<0); /* Threshold is 256 */ do { writel(req_reg, AHB2STBUS_STBUS_CONFIG); reg = readl(AHB2STBUS_STBUS_CONFIG); } while ((reg & 0x7FFFFFFF) != req_reg); #endif /* QQQ - TO DO */ }
static void configEthernet(void) { /* Setup PIO for the PHY's reset */ SET_PIO_PIN(PIO_PORT(1),6,STPIO_OUT); /* PHY_RES is on PIO1[6] */ /* Finally, just toggle the PHY Reset pin */ STPIO_SET_PIN(PIO_PORT(1), 6, 0); /* Assert PHY_RES */ udelay(100); /* small delay (100us) */ STPIO_SET_PIN(PIO_PORT(1), 6, 1); /* de-assert PHY_RES */ }
extern void fli7510_i2c_sda(const int val) { #if defined(CONFIG_I2C_BUS_1) /* Use I2C Bus "1" */ STPIO_SET_PIN(PIO_PORT(10), 3, (val) ? 1 : 0); #elif defined(CONFIG_I2C_BUS_2) /* Use I2C Bus "2" */ STPIO_SET_PIN(PIO_PORT(9), 5, (val) ? 1 : 0); #elif defined(CONFIG_I2C_BUS_3) /* Use I2C Bus "3" */ STPIO_SET_PIN(PIO_PORT(9), 7, (val) ? 1 : 0); #endif }
extern int fli7510_i2c_read(void) { #if defined(CONFIG_I2C_BUS_1) /* Use I2C Bus "1" */ return STPIO_GET_PIN(PIO_PORT(10), 3); #elif defined(CONFIG_I2C_BUS_2) /* Use I2C Bus "2" */ return STPIO_GET_PIN(PIO_PORT(9), 5); #elif defined(CONFIG_I2C_BUS_3) /* Use I2C Bus "3" */ return STPIO_GET_PIN(PIO_PORT(9), 7); #endif }
static void configSpi(void) { unsigned long sysconf; /* * CONFIG_SYS_COMMS_CONFIG_2[13] = spi_enable = 0 * i.e. disable the SPI boot-controller. */ sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2); sysconf &= ~(1ul<<13); writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2); /* * For both S/W "bit-banging" and H/W SSC, the SPI is on PIO17[5:0]. * Now, we set up the PIO pins correctly. */ SET_PIO_PIN(PIO_PORT(17),5,STPIO_IN); /* SPI_MISO */ SET_PIO_PIN(PIO_PORT(17),4,STPIO_OUT); /* SPI_CSN */ #if defined(CONFIG_SOFT_SPI) /* Configure SPI Serial Flash for PIO "bit-banging" */ SET_PIO_PIN(PIO_PORT(17),2,STPIO_OUT); /* SPI_CLK */ SET_PIO_PIN(PIO_PORT(17),3,STPIO_OUT); /* SPI_MOSI */ #elif defined(CONFIG_STM_SSC_SPI) /* Use the H/W SSC for SPI */ SET_PIO_PIN(PIO_PORT(17),2,STPIO_ALT_OUT);/* SPI_CLK */ SET_PIO_PIN(PIO_PORT(17),3,STPIO_ALT_OUT);/* SPI_MOSI */ #endif /* CONFIG_SOFT_SPI */ /* drive (non-SSC) outputs with sensible initial values */ STPIO_SET_PIN(PIO_PORT(17), 4, 1); /* deassert SPI_CSN */ #if defined(CONFIG_SOFT_SPI) STPIO_SET_PIN(PIO_PORT(17), 2, 1); /* assert SPI_CLK */ STPIO_SET_PIN(PIO_PORT(17), 3, 0); /* deassert SPI_MOSI */ #endif /* CONFIG_SOFT_SPI */ }
static void configSerial (void) { #if (CONFIG_SYS_STM_ASC_BASE == ST40_ASC0_REGS_BASE) /* UART #1 */ /* Route UART #1 via PIO9 for TX, RX, CTS & RTS */ SET_PIO_ASC(PIO_PORT(9), 3, 2, 1, 0); #elif (CONFIG_SYS_STM_ASC_BASE == ST40_ASC1_REGS_BASE) /* UART #2 */ /* Route UART #2 via PIO25 for TX, RX, CTS & RTS */ SET_PIO_ASC(PIO_PORT(25), 5, 4, 3, 2); #elif (CONFIG_SYS_STM_ASC_BASE == ST40_ASC2_REGS_BASE) /* UART #3 */ /* Route UART #3 via PIO25 for TX & RX */ SET_PIO_ASC(PIO_PORT(25), 7, 6, STPIO_NO_PIN, STPIO_NO_PIN); #else #error Unknown serial port configuration! #endif }
extern void spi_cs_deactivate(struct spi_slave * const slave) { const int pin = 4; /* PIO17[4] = SPI_CSN */ /* DE-assert SPI CSn */ STPIO_SET_PIN(PIO_PORT(17), pin, 1); }
void pio_write() { uint8_t data, cfm; while(! errno) { data = ows_recv(); cfm = ~ows_recv(); if(cfm != data) break; data = ~((data & 0x01) | ((data &0x02) << 1)); data |= PIO_PORT(DDR) & ~0x05; PIO_PORT(DDR) = data; ows_send(0xAA); pio_send_state(); } }
void button_bad_polling(struct work_struct *ignored) #endif { while(bad_polling == 1) { msleep(50); button_value = (STPIO_GET_PIN(PIO_PORT(1),0) <<2) | (STPIO_GET_PIN(PIO_PORT(1),1) <<1) | (STPIO_GET_PIN(PIO_PORT(1),2) <<0); if (button_value != 7) { switch(button_value) { // v-format case 6: { input_report_key(button_dev, BTN_0, 1); input_sync(button_dev); break; } // menu case 4: { input_report_key(button_dev, BTN_1, 1); input_sync(button_dev); break; } // option case 3: { input_report_key(button_dev, BTN_2, 1); input_sync(button_dev); break; } // exit case 5: { input_report_key(button_dev, BTN_3, 1); input_sync(button_dev); break; } default: dprintk("[BTN] unknown button_value?"); } } else { input_report_key(button_dev, BTN_0, 0); input_report_key(button_dev, BTN_1, 0); input_report_key(button_dev, BTN_2, 0); input_report_key(button_dev, BTN_3, 0); input_sync(button_dev); } } }
/* * assert or de-assert the SPI Chip Select line. * * input: cs == true, assert CS, else deassert CS */ static void spi_chip_select(const int cs) { const int pin = 2; /* PIO15[2] = SPI_NOTCS */ if (cs) { /* assert SPI CSn */ STPIO_SET_PIN(PIO_PORT(15), pin, 0); } else { /* DE-assert SPI CSn */ STPIO_SET_PIN(PIO_PORT(15), pin, 1); } if (cs) { /* wait 250ns for CSn assert to propagate */ udelay(1); /* QQQ: can we make this shorter ? */ } }
void pio_send_state() { /* | 7 6 5 4 | 3 2 1 0 | |<complement of 3-0>|OutB PinB OutA PinA | */ uint8_t sample = PIO_PORT(PIN) & 0x05; /* output values is inversion of direction register */ sample |= (((~PIO_PORT(DDR)) & 0x05) << 1); sample |= (~sample << 4); ows_send(sample); }
/* * A pair of functions to assert and de-assert the SPI * chip select line, for the given SPI "slave" device. * * This is used by both the S/W "bit-banging" and the * H/W SSC drivers (but not the H/W FSM driver). * * We only support *one* SPI device, so we just ignore * the "slave" parameter. This may change later... */ extern void spi_cs_activate(struct spi_slave * const slave) { const int pin = 4; /* PIO17[4] = SPI_CSN */ /* assert SPI CSn */ STPIO_SET_PIN(PIO_PORT(17), pin, 0); /* wait 1us for CSn assert to propagate */ udelay(1); }
int main() { wdt_disable(); #if defined(__AVR_ATtiny85__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny13__) CLKPR = 0x80; /* Clock prescaler change enable */ CLKPR = 0x00; /* Division Factor = 1, system clock 9.6MHz */ #endif ows_setup(myrom); PIO_PORT(PORT) = 0; for(;;) ows_wait_request(); }
static void configPIO(void) { unsigned long sysconf; /* Setup PIO of ASC device */ SET_PIO_ASC(PIO_PORT(10), 0, 1, 2, 3); /* ASC1 */ SET_PIO_ASC(PIO_PORT(6), 0, 1, 2, 3); /* ASC2 */ /* Enable ASC UARTS */ sysconf = *STX7141_SYSCONF_SYS_CFG36; /* CFG36[29] = 0 = UART1_CTRL_NOT_MII_SEL */ sysconf &= 1ul << 29; /* CFG36[30] = 1 = UART2_CTS_SEL */ /* CFG36[31] = 1 = UART2_RXD_SEL */ sysconf |= 1ul << 30 | 1ul << 31; *STX7141_SYSCONF_SYS_CFG36 = sysconf; /* Route ASC1 via PIO[10] for TX, RX, CTS & RTS */ sysconf = *STX7141_SYSCONF_SYS_CFG46; /* PIO10[0] Selector: CFG46[7:6] = 3 */ /* PIO10[1] Selector: CFG46[9:8] = 3 */ /* PIO10[2] Selector: CFG46[11:10] = 3 */ /* PIO10[3] Selector: CFG46[13:12] = 3 */ sysconf |= 3ul << 6 | 3ul << 8 | 3ul << 10 | 3ul << 12; *STX7141_SYSCONF_SYS_CFG46 = sysconf; /* Route ASC2 via PIO[6] for TX & RX */ sysconf = *STX7141_SYSCONF_SYS_CFG20; /* PIO6[0] Selector: CFG20[28:27] = 3 */ /* PIO6[0] Selector: CFG20[30:29] = 3 */ sysconf |= 3ul << 27 | 3ul << 29; *STX7141_SYSCONF_SYS_CFG20 = sysconf; /* Route ASC2 via PIO[6] for CTS & RTS */ sysconf = *STX7141_SYSCONF_SYS_CFG25; /* PIO6[0] Selector: CFG25[1:0] = 3 */ /* PIO6[0] Selector: CFG25[3:2] = 3 */ sysconf |= 3ul << 0 | 3ul << 2; *STX7141_SYSCONF_SYS_CFG25 = sysconf; }
static void configPIO(void) { /* Setup PIO of ASC device */ #if CFG_STM_ASC_BASE == ST40_ASC2_REGS_BASE /* UART #2 */ SET_PIO_ASC(PIO_PORT(4), 3, 2, 4, 5); /* UART2 - AS0 */ #else #error Unsure which UART to configure! #endif /* CFG_STM_ASC_BASE == ST40_ASC2_REGS_BASE */ /* Configure & Reset the Ethernet PHY */ configEthernet(); #if defined(CONFIG_SPI) /* Configure for SPI Serial Flash */ configSpi(); #endif /* CONFIG_SPI */ }
static void configSpi(void) { #if defined(CONFIG_SOFT_SPI) /* Configure SPI Serial Flash for PIO "bit-banging" */ /* SPI is on PIO2[2:0], with CS on PIO6[7] */ SET_PIO_PIN(PIO_PORT(2),0,STPIO_OUT); /* SPI_CLK */ SET_PIO_PIN(PIO_PORT(2),1,STPIO_OUT); /* SPI_DOUT */ SET_PIO_PIN(PIO_PORT(2),2,STPIO_IN); /* SPI_DIN */ SET_PIO_PIN(PIO_PORT(6),7,STPIO_OUT); /* SPI_NOTCS */ /* drive outputs with sensible initial values */ STPIO_SET_PIN(PIO_PORT(6), 7, 1); /* deassert SPI_NOCS */ STPIO_SET_PIN(PIO_PORT(2), 0, 1); /* assert SPI_CLK */ STPIO_SET_PIN(PIO_PORT(2), 1, 0); /* deassert SPI_DOUT */ #else #error Still to impliment SPI via SSC for the STx7111. #endif /* CONFIG_SOFT_SPI */ }
static void configPIO(void) { /* Setup PIO of ASC device */ SET_PIO_ASC(PIO_PORT(4), 3, 2, 4, 5); /* UART2 - AS0 */ SET_PIO_ASC(PIO_PORT(5), 4, 3, 5, 6); /* UART3 - AS1 */ #ifdef CONFIG_DRIVER_NETSTMAC /* Reset the on-board STe101P PHY */ SET_PIO_PIN(PIO_PORT(4), 7, STPIO_OUT); STPIO_SET_PIN(PIO_PORT(4), 7, 1); udelay(1); STPIO_SET_PIN(PIO_PORT(4), 7, 0); udelay(1); STPIO_SET_PIN(PIO_PORT(4), 7, 1); #endif /* CONFIG_DRIVER_NETSTMAC */ #if defined(CONFIG_CMD_NAND) /* Setup PIO for NAND FLASH devices: Ready/Not_Busy */ SET_PIO_PIN(PIO_PORT(2), 7, STPIO_IN); #endif /* CONFIG_CMD_NAND */ }
static void configI2c(void) { /* * The I2C busses are routed as follows: * * Bus SCL SDA * --- --- --- * 1 PIO10[2] PIO10[3] * 2 PIO9[4] PIO9[5] * 3 PIO9[6] PIO9[7] */ #if defined(CONFIG_I2C_BUS_1) /* Use I2C Bus "1" */ SET_PIO_PIN(PIO_PORT(10),2,STPIO_BIDIR);/* I2C1_SCL */ SET_PIO_PIN(PIO_PORT(10),3,STPIO_BIDIR);/* I2C1_SDA */ #elif defined(CONFIG_I2C_BUS_2) /* Use I2C Bus "2" */ SET_PIO_PIN(PIO_PORT(9),4,STPIO_BIDIR); /* I2C2_SCL */ SET_PIO_PIN(PIO_PORT(9),5,STPIO_BIDIR); /* I2C2_SDA */ #elif defined(CONFIG_I2C_BUS_3) /* Use I2C Bus "3" */ SET_PIO_PIN(PIO_PORT(9),6,STPIO_BIDIR); /* I2C3_SCL */ SET_PIO_PIN(PIO_PORT(9),7,STPIO_BIDIR); /* I2C3_SDA */ #else #error Unknown I2C Bus! #endif }
void stx7105_led_write(int led) { const int pin = 4; /* PIO0[1] = */ STPIO_SET_PIN(PIO_PORT(0), pin,led); //gongjia mark }
extern void fli7510_spi_sda(const int val) { const int pin = 3; /* PIO17[3] = SPI_MOSI */ STPIO_SET_PIN(PIO_PORT(17), pin, val ? 1 : 0); }
/* ETH MAC pad configuration */ static void stmac_eth_hw_setup( int reverse_mii, int rmii_mode, int mode, int ext_mdio, int ext_clk, int phy_bus) { unsigned long sysconf; sysconf = *STX7105_SYSCONF_SYS_CFG07; /* Ethernet ON */ sysconf |= (ETHERNET_INTERFACE_ON); /* MII M-DIO select: 1: miim_dio from external input, 0: from GMAC */ if (ext_mdio) sysconf |= (EXT_MDIO); else sysconf &= ~(EXT_MDIO); /* RMII pin multiplexing: 0: MII interface active, 1: RMII interface */ /* cut 1: This register was not connected, so only MII available */ if (rmii_mode) sysconf |= (RMII_MODE); else sysconf &= ~(RMII_MODE); /* * PHY EXT CLOCK: 0: provided by STx7105; 1: external * cut 1: sysconf7[19], however this was not connected, so only * input supported. * cut 2: direction now based on PIO direction, so this code removed. */ /* Default GMII/MII selection */ sysconf &= ~(PHY_INTF_SEL_MASK); sysconf |= ((mode&3ul)<<25); /* MII mode */ if (reverse_mii) sysconf &= ~(ENMII); else sysconf |= (ENMII); *STX7105_SYSCONF_SYS_CFG07 = sysconf; /* Pin configuration... */ /* PIO7[4] CFG37[8+4,4] = Alternate1 = MIIRX_DV/MII_EXCRS */ /* PIO7[5] CFG37[8+5,5] = Alternate1 = MIIRX_ER/MII_EXCOL */ /* PIO7[6] CFG37[8+6,6] = Alternate1 = MIITXD[0] */ /* PIO7[7] CFG37[8+7,7] = Alternate1 = MIITXD[1] */ sysconf = *STX7105_SYSCONF_SYS_CFG37; sysconf &= ~(0xf0f0ul); /* Mask=3,3,3,3 */ sysconf |= 0x0000ul; /* OR =0,0,0,0 */ *STX7105_SYSCONF_SYS_CFG37 = sysconf; SET_PIO_PIN(PIO_PORT(7), 4, STPIO_IN); SET_PIO_PIN(PIO_PORT(7), 5, STPIO_IN); SET_PIO_PIN(PIO_PORT(7), 6, STPIO_ALT_OUT); SET_PIO_PIN(PIO_PORT(7), 7, STPIO_ALT_OUT); /* PIO8[0] CFG46[8+0,0] = Alternate1 = MIITXD[2] */ /* PIO8[1] CFG46[8+1,1] = Alternate1 = MIITXD[3] */ /* PIO8[2] CFG46[8+2,2] = Alternate1 = MIITX_EN */ /* PIO8[3] CFG46[8+3,3] = Alternate1 = MIIMDIO */ /* PIO8[4] CFG46[8+4,4] = Alternate1 = MIIMDC */ /* PIO8[5] CFG46[8+5,5] = Alternate1 = MIIRXCLK */ /* PIO8[6] CFG46[8+6,6] = Alternate1 = MIIRXD[0] */ /* PIO8[7] CFG46[8+7,7] = Alternate1 = MIIRXD[1] */ sysconf = *STX7105_SYSCONF_SYS_CFG46; sysconf &= ~(0xfffful); /* Mask=3,3,3,3,3,3,3,3 */ sysconf |= 0x0000ul; /* OR =0,0,0,0,0,0,0,0 */ *STX7105_SYSCONF_SYS_CFG46 = sysconf; SET_PIO_PIN(PIO_PORT(8), 0, STPIO_ALT_OUT); SET_PIO_PIN(PIO_PORT(8), 1, STPIO_ALT_OUT); SET_PIO_PIN(PIO_PORT(8), 2, STPIO_ALT_OUT); SET_PIO_PIN(PIO_PORT(8), 3, STPIO_ALT_BIDIR); SET_PIO_PIN(PIO_PORT(8), 4, STPIO_ALT_OUT); SET_PIO_PIN(PIO_PORT(8), 5, STPIO_IN); SET_PIO_PIN(PIO_PORT(8), 6, STPIO_IN); SET_PIO_PIN(PIO_PORT(8), 7, STPIO_IN); /* PIO9[0] CFG47[8+0,0] = Alternate1 = MIIRXD[2] */ /* PIO9[1] CFG47[8+1,1] = Alternate1 = MIIRXD[3] */ /* PIO9[2] CFG47[8+2,2] = Alternate1 = MIITXCLK */ /* PIO9[3] CFG47[8+3,3] = Alternate1 = MIICOL */ /* PIO9[4] CFG47[8+4,4] = Alternate1 = MIICRS */ /* PIO9[5] CFG47[8+5,5] = Alternate1 = MIIPHYCLK */ /* PIO9[6] CFG47[8+6,6] = Alternate1 = MIIMDINT */ sysconf = *STX7105_SYSCONF_SYS_CFG47; sysconf &= ~(0x7f7ful); /* Mask=3,3,3,3,3,3,3 */ sysconf |= 0x0000ul; /* OR =0,0,0,0,0,0,0 */ *STX7105_SYSCONF_SYS_CFG47 = sysconf; SET_PIO_PIN(PIO_PORT(9), 0, STPIO_IN); SET_PIO_PIN(PIO_PORT(9), 1, STPIO_IN); SET_PIO_PIN(PIO_PORT(9), 2, STPIO_IN); SET_PIO_PIN(PIO_PORT(9), 3, STPIO_IN); SET_PIO_PIN(PIO_PORT(9), 4, STPIO_IN); /* MIIPHYCLK */ /* Not implemented in cut 1 (DDTS GNBvd69906) - clock never output */ /* In cut 2 PIO direction used to control input or output. */ if (ext_clk) SET_PIO_PIN(PIO_PORT(9), 5, STPIO_IN); else SET_PIO_PIN(PIO_PORT(9), 5, STPIO_ALT_OUT); SET_PIO_PIN(PIO_PORT(9), 6, STPIO_IN); }
extern unsigned char stx7105_spi_read(void) { const int pin = 3; /* PIO15[3] = SPI_DIN */ return STPIO_GET_PIN(PIO_PORT(15), pin); }
extern void stx7105_spi_sda(const int val) { const int pin = 1; /* PIO15[1] = SPI_DOUT */ STPIO_SET_PIN(PIO_PORT(15), pin, val ? 1 : 0); }
/* configure the SATA host controller */ stm_sata_probe(); initialised_phy = 1; } } #endif /* CONFIG_SH_STM_SATA */ #if defined(CONFIG_SPI) #if defined(CONFIG_SOFT_SPI) /* Use "bit-banging" for SPI */ extern void stx7105_spi_scl(const int val) { const int pin = 0; /* PIO15[0] = SPI_CLK */ STPIO_SET_PIN(PIO_PORT(15), pin, val ? 1 : 0); }
extern unsigned char fli7510_spi_read(void) { const int pin = 5; /* PIO17[5] = SPI_MISO */ return STPIO_GET_PIN(PIO_PORT(17), pin); }
extern unsigned char stx7105_key_read(void) { const int pin = 1; /* PIO0[1] = */ return STPIO_GET_PIN(PIO_PORT(0), pin); //gongjia mark }