static void
ppbattach(device_t parent, device_t self, void *aux)
{
struct ppb_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
struct pcibus_attach_args pba;
pcireg_t busdata;
pci_aprint_devinfo(pa, NULL);
sc->sc_pc = pc;
sc->sc_tag = pa->pa_tag;
sc->sc_dev = self;
busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
aprint_normal_dev(self, "not configured by system firmware\n");
return;
}
ppb_fix_pcie(self);
#if 0
/*
* XXX can't do this, because we're not given our bus number
* (we shouldn't need it), and because we've no way to
* decompose our tag.
*/
/* sanity check. */
if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
#endif
if (!pmf_device_register(self, ppb_suspend, ppb_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
/*
* Attach the PCI bus than hangs off of it.
*
* XXX Don't pass-through Memory Read Multiple. Should we?
* XXX Consult the spec...
*/
pba.pba_iot = pa->pa_iot;
pba.pba_memt = pa->pa_memt;
pba.pba_dmat = pa->pa_dmat;
pba.pba_dmat64 = pa->pa_dmat64;
pba.pba_pc = pc;
pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata);
pba.pba_bridgetag = &sc->sc_tag;
pba.pba_intrswiz = pa->pa_intrswiz;
pba.pba_intrtag = pa->pa_intrtag;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
static int
i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset,
struct pciconf_state *ps)
{
pcireg_t binfo;
int pbus, sbus;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return (1);
i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
pbus = PPB_BUSINFO_PRIMARY(binfo);
sbus = PPB_BUSINFO_SECONDARY(binfo);
/*
* If the bus # is the Primary bus #, use the Primary
* Address/Data registers, otherwise use the Secondary
* Address/Data registers.
*/
if (ps->ps_b == pbus) {
ps->ps_addr_reg = I80312_ATU_POCCA;
ps->ps_data_reg = I80312_ATU_POCCD;
ps->ps_csr_reg = PCI_COMMAND_STATUS_REG;
} else {
ps->ps_addr_reg = I80312_ATU_SOCCA;
ps->ps_data_reg = I80312_ATU_SOCCD;
ps->ps_csr_reg = I80312_ATU_SACS;
}
/*
* If the bus # is the Primary or Secondary bus #, then use
* Type 0 cycles, else use Type 1.
*
* XXX We should filter out all non-private devices here!
* XXX How does private space interact with PCI-PCI bridges?
*/
if (ps->ps_b == pbus || ps->ps_b == sbus) {
if (ps->ps_d > (31 - 11))
return (1);
ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) |
offset;
} else {
/* The tag is already in the correct format. */
ps->ps_addr_val = tag | offset | 1;
}
return (0);
}
void
i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80312_softc *sc = cookie;
struct extent *ioext, *memext;
pcireg_t binfo;
int sbus;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = i80312_pci_attach_hook;
pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
pc->pc_make_tag = i80312_pci_make_tag;
pc->pc_decompose_tag = i80312_pci_decompose_tag;
pc->pc_conf_read = i80312_pci_conf_read;
pc->pc_conf_write = i80312_pci_conf_write;
pc->pc_conf_interrupt = i80312_pci_conf_interrupt;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
/* pbus = PPB_BUSINFO_PRIMARY(binfo); */
sbus = PPB_BUSINFO_SECONDARY(binfo);
ioext = extent_create("pciio", sc->sc_sioout_base,
sc->sc_sioout_base + sc->sc_sioout_size - 1,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", sc->sc_smemout_base,
sc->sc_smemout_base + sc->sc_smemout_size - 1,
NULL, 0, EX_NOWAIT);
aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
int
iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
pcireg_t reg;
int sbus;
/*
* The Npwr routes #INTA of the on-board PCI devices directly
* through the CPLD. There is no PCI-PCI bridge and no PCI
* slots on the Npwr.
*
* We also expect the devices to be on the Secondary side of
* the i80312.
*/
reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
sbus = PPB_BUSINFO_SECONDARY(reg);
if (pa->pa_bus != sbus) {
printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
switch (pa->pa_device) {
case 5: /* LSI 53c1010 SCSI */
*ihp = XINT3_IRQ(2);
break;
case 6: /* Intel i82544GC Gig-E #1 */
*ihp = XINT3_IRQ(1);
break;
case 7: /* Intel i82544GC Gig-E #2 */
*ihp = XINT3_IRQ(4);
break;
default:
printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
return (0);
}
void
ppb_alloc_resources(struct ppb_softc *sc, struct pci_attach_args *pa)
{
pci_chipset_tag_t pc = sc->sc_pc;
pcireg_t id, busdata, blr, bhlcr, type, csr;
pcireg_t addr, mask;
pcitag_t tag;
int bus, dev;
int reg, reg_start, reg_end, reg_rom;
int io_count = 0;
int mem_count = 0;
bus_addr_t start, end;
u_long base, size;
if (pa->pa_memex == NULL)
return;
busdata = pci_conf_read(pc, sc->sc_tag, PPB_REG_BUSINFO);
bus = PPB_BUSINFO_SECONDARY(busdata);
if (bus == 0)
return;
/*
* Count number of devices. If there are no devices behind
* this bridge, there's no point in allocating any address
* space.
*/
for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) {
tag = pci_make_tag(pc, bus, dev, 0);
id = pci_conf_read(pc, tag, PCI_ID_REG);
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID ||
PCI_VENDOR(id) == 0)
continue;
bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
switch (PCI_HDRTYPE_TYPE(bhlcr)) {
case 0:
reg_start = PCI_MAPREG_START;
reg_end = PCI_MAPREG_END;
reg_rom = PCI_ROM_REG;
break;
case 1: /* PCI-PCI bridge */
reg_start = PCI_MAPREG_START;
reg_end = PCI_MAPREG_PPB_END;
reg_rom = 0; /* 0x38 */
break;
case 2: /* PCI-Cardbus bridge */
reg_start = PCI_MAPREG_START;
reg_end = PCI_MAPREG_PCB_END;
reg_rom = 0;
break;
default:
return;
}
for (reg = reg_start; reg < reg_end; reg += 4) {
if (pci_mapreg_probe(pc, tag, reg, &type) == 0)
continue;
if (type == PCI_MAPREG_TYPE_IO)
io_count++;
else
mem_count++;
}
if (reg_rom != 0) {
addr = pci_conf_read(pc, tag, reg_rom);
pci_conf_write(pc, tag, reg_rom, ~PCI_ROM_ENABLE);
mask = pci_conf_read(pc, tag, reg_rom);
pci_conf_write(pc, tag, reg_rom, addr);
if (PCI_ROM_SIZE(mask))
mem_count++;
}
}
csr = pci_conf_read(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
/*
* Get the bridge in a consistent state. If memory mapped I/O
* is disabled, disabled the associated windows as well.
*/
if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) {
pci_conf_write(pc, sc->sc_tag, PPB_REG_MEM, 0x0000ffff);
pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFMEM, 0x0000ffff);
pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFBASE_HI32, 0);
pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFLIM_HI32, 0);
}
/* Allocate I/O address space if necessary. */
if (io_count > 0 && pa->pa_ioex) {
blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IOSTATUS);
sc->sc_iobase = (blr << PPB_IO_SHIFT) & PPB_IO_MASK;
sc->sc_iolimit = (blr & PPB_IO_MASK) | 0x00000fff;
blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IO_HI);
sc->sc_iobase |= (blr & 0x0000ffff) << 16;
sc->sc_iolimit |= (blr & 0xffff0000);
if (sc->sc_iolimit < sc->sc_iobase || sc->sc_iobase == 0) {
start = max(PCI_IO_START, pa->pa_ioex->ex_start);
end = min(PCI_IO_END, pa->pa_ioex->ex_end);
for (size = 0x2000; size >= PPB_IO_MIN; size >>= 1)
if (extent_alloc_subregion(pa->pa_ioex, start,
end, size, size, 0, 0, 0, &base) == 0)
break;
if (size >= PPB_IO_MIN) {
sc->sc_iobase = base;
sc->sc_iolimit = base + size - 1;
blr = pci_conf_read(pc, sc->sc_tag,
PPB_REG_IOSTATUS);
blr &= 0xffff0000;
blr |= sc->sc_iolimit & PPB_IO_MASK;
blr |= (sc->sc_iobase >> PPB_IO_SHIFT);
pci_conf_write(pc, sc->sc_tag,
PPB_REG_IOSTATUS, blr);
blr = (sc->sc_iobase & 0xffff0000) >> 16;
blr |= sc->sc_iolimit & 0xffff0000;
pci_conf_write(pc, sc->sc_tag,
PPB_REG_IO_HI, blr);
csr |= PCI_COMMAND_IO_ENABLE;
}
void
ppbattach(struct device *parent, struct device *self, void *aux)
{
struct ppb_softc *sc = (struct ppb_softc *)self;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
struct pcibus_attach_args pba;
pci_intr_handle_t ih;
pcireg_t busdata, reg, blr;
char *name;
int pin;
sc->sc_pc = pc;
sc->sc_tag = pa->pa_tag;
busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
printf(": not configured by system firmware\n");
return;
}
#if 0
/*
* XXX can't do this, because we're not given our bus number
* (we shouldn't need it), and because we've no way to
* decompose our tag.
*/
/* sanity check. */
if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
#endif
/* Check for PCI Express capabilities and setup hotplug support. */
if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
&sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) {
#ifdef __i386__
if (pci_intr_map(pa, &ih) == 0)
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO,
ppb_intr, sc, self->dv_xname);
#else
if (pci_intr_map_msi(pa, &ih) == 0 ||
pci_intr_map(pa, &ih) == 0)
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO,
ppb_intr, sc, self->dv_xname);
#endif
if (sc->sc_intrhand) {
printf(": %s", pci_intr_string(pc, ih));
/* Enable hotplug interrupt. */
reg = pci_conf_read(pc, pa->pa_tag,
sc->sc_cap_off + PCI_PCIE_SLCSR);
reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE);
pci_conf_write(pc, pa->pa_tag,
sc->sc_cap_off + PCI_PCIE_SLCSR, reg);
timeout_set(&sc->sc_to, ppb_hotplug_insert_finish, sc);
}
}
printf("\n");
if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL ||
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82801BA_HPB &&
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82801BAM_HPB))
ppb_alloc_resources(sc, pa);
for (pin = PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_D; pin++) {
pa->pa_intrpin = pa->pa_rawintrpin = pin;
pa->pa_intrline = 0;
pci_intr_map(pa, &sc->sc_ih[pin - PCI_INTERRUPT_PIN_A]);
}
/*
* The UltraSPARC-IIi APB doesn't implement the standard
* address range registers.
*/
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA)
goto attach;
/* Figure out the I/O address range of the bridge. */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS);
sc->sc_iobase = (blr & 0x000000f0) << 8;
sc->sc_iolimit = (blr & 0x000f000) | 0x00000fff;
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IO_HI);
sc->sc_iobase |= (blr & 0x0000ffff) << 16;
sc->sc_iolimit |= (blr & 0xffff0000);
if (sc->sc_iolimit > sc->sc_iobase) {
name = malloc(32, M_DEVBUF, M_NOWAIT);
if (name) {
snprintf(name, 32, "%s pciio", sc->sc_dev.dv_xname);
sc->sc_ioex = extent_create(name, 0, 0xffffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
extent_free(sc->sc_ioex, sc->sc_iobase,
sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT);
}
}
/* Figure out the memory mapped I/O address range of the bridge. */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_MEM);
sc->sc_membase = (blr & 0x0000fff0) << 16;
sc->sc_memlimit = (blr & 0xfff00000) | 0x000fffff;
if (sc->sc_memlimit > sc->sc_membase) {
name = malloc(32, M_DEVBUF, M_NOWAIT);
if (name) {
snprintf(name, 32, "%s pcimem", sc->sc_dev.dv_xname);
sc->sc_memex = extent_create(name, 0, 0xffffffff,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
extent_free(sc->sc_memex, sc->sc_membase,
sc->sc_memlimit - sc->sc_membase + 1,
EX_NOWAIT);
}
}
/* Figure out the prefetchable MMI/O address range of the bridge. */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFMEM);
sc->sc_pmembase = (blr & 0x0000fff0) << 16;
sc->sc_pmemlimit = (blr & 0xfff00000) | 0x000fffff;
#ifdef __LP64__ /* XXX because extents use long... */
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32);
sc->sc_pmembase |= ((uint64_t)blr) << 32;
blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32);
sc->sc_pmemlimit |= ((uint64_t)blr) << 32;
#endif
if (sc->sc_pmemlimit > sc->sc_pmembase) {
name = malloc(32, M_DEVBUF, M_NOWAIT);
if (name) {
snprintf(name, 32, "%s pcipmem", sc->sc_dev.dv_xname);
sc->sc_pmemex = extent_create(name, 0, (u_long)-1L,
M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
extent_free(sc->sc_pmemex, sc->sc_pmembase,
sc->sc_pmemlimit - sc->sc_pmembase + 1,
EX_NOWAIT);
}
}
/*
* The Intel 82801BAM Hub-to-PCI can decode subtractively.
* XXX We probably should handle subtractive decode bridges
* in general.
*/
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BA_HPB ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_HPB)) {
if (sc->sc_ioex == NULL)
sc->sc_ioex = pa->pa_ioex;
if (sc->sc_memex == NULL)
sc->sc_memex = pa->pa_memex;
}
attach:
/*
* Attach the PCI bus that hangs off of it.
*
* XXX Don't pass-through Memory Read Multiple. Should we?
* XXX Consult the spec...
*/
bzero(&pba, sizeof(pba));
pba.pba_busname = "pci";
pba.pba_iot = pa->pa_iot;
pba.pba_memt = pa->pa_memt;
pba.pba_dmat = pa->pa_dmat;
pba.pba_pc = pc;
pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
pba.pba_ioex = sc->sc_ioex;
pba.pba_memex = sc->sc_memex;
pba.pba_pmemex = sc->sc_pmemex;
pba.pba_domain = pa->pa_domain;
pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
pba.pba_bridgeih = sc->sc_ih;
pba.pba_bridgetag = &sc->sc_tag;
pba.pba_intrswiz = pa->pa_intrswiz;
pba.pba_intrtag = pa->pa_intrtag;
sc->sc_psc = config_found(self, &pba, ppbprint);
}
/*
* The Npwr routes #INTA of the on-board PCI devices directly
* through the CPLD. There is no PCI-PCI bridge and no PCI
* slots on the Npwr.
*
* We also expect the devices to be on the Secondary side of
* the i80312.
*/
reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
sbus = PPB_BUSINFO_SECONDARY(reg);
if (pa->pa_bus != sbus) {
printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
switch (pa->pa_device) {
case 5: /* LSI 53c1010 SCSI */
*ihp = XINT3_IRQ(2);
break;
case 6: /* Intel i82544GC Gig-E #1 */
*ihp = XINT3_IRQ(1);
break;
case 7: /* Intel i82544GC Gig-E #2 */
*ihp = XINT3_IRQ(4);
break;
default:
printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n",
pa->pa_bus, pa->pa_device, pa->pa_function);
return (1);
}
return (0);
}
#else /* Default to stock IQ80310 */
int
iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
pcitag_t tag;
pcireg_t reg;
int sbus, pbus;
/*
* Mapping of PCI interrupts on the IQ80310 is pretty easy; there
* is a single interrupt line for all PCI devices on pre-F boards,
* and an interrupt line for each INTx# signal on F and later boards.
*
* The only exception is the on-board Ethernet; this devices has
* its own dedicated interrupt line. The location of this device
* looks like this:
*
* 80312 Secondary -> PPB at dev #7 -> i82559 at dev #0
*
* In order to determine if we're mapping the interrupt for the
* on-board Ethernet, we must read the Secondary Bus # of the
* i80312, then use that to read the Secondary Bus # of the
* 21154 PPB. At that point, we know that b/d/f of the i82559,
* and can determine if we're looking at that device.
*/
reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
pbus = PPB_BUSINFO_PRIMARY(reg);
sbus = PPB_BUSINFO_SECONDARY(reg);
/*
* XXX We don't know how to map interrupts on the Primary
* XXX PCI bus right now.
*/
if (pa->pa_bus == pbus) {
printf("iq80310_pci_intr_map: can't map interrupts on "
"Primary bus\n");
return (1);
}
tag = pci_make_tag(pa->pa_pc, sbus, 7, 0);
/* Make sure the PPB is there. */
reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
PCI_VENDOR(reg) == 0) {
/*
* That's odd... no PPB there? Oh well, issue a warning
* and continue on.
*/
printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n",
sbus, 7, 0);
goto pinmap;
}
/* Make sure the device that's there is a PPB. */
reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) {
/*
* That's odd... the device that's there isn't a PPB.
* Oh well, issue a warning and continue on.
*/
printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n",
sbus, 7, 0);
goto pinmap;
}
/* Now read the PPB's secondary bus number. */
reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO);
sbus = PPB_BUSINFO_SECONDARY(reg);
if (pa->pa_bus == sbus && pa->pa_device == 0 &&
pa->pa_function == 0) {
/* On-board i82559 Ethernet! */
*ihp = XINT3_IRQ(XINT3_ETHERNET);
return (0);
}
pinmap:
if (pa->pa_intrpin == 0) {
/* No IRQ used. */
return (1);
}
if (pa->pa_intrpin > 4) {
printf("iq80310_pci_intr_map: bad interrupt pin %d\n",
pa->pa_intrpin);
return (1);
}
/* INTD# is always in XINT3. */
if (pa->pa_intrpin == 4) {
*ihp = XINT3_IRQ(XINT3_SINTD);
return (0);
}
/* On pre-F boards, ALL of them are on XINT3. */
if (/*pre-F*/0)
*ihp = XINT3_IRQ(XINT3_SINTD);
else
*ihp = XINT0_IRQ(pa->pa_intrpin - 1);
return (0);
}