//*****************************************************************************
//
//! Configure the audio clock generation with manual setting of clock divider.
//
//*****************************************************************************
void
PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
uint32_t ui32BitDiv, uint32_t ui32WordDiv)
{
uint32_t ui32Reg;
//
// Check the arguments.
//
ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
//
// Make sure the audio clock generation is disabled before reconfiguring.
//
PRCMAudioClockDisable();
//
// Make sure to compensate the Frame clock division factor if using single
// phase format.
//
if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
{
ui32WordDiv -= 1;
}
//
// Write the clock division factors.
//
HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
//
// Configure the Word clock format and polarity.
//
ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}
//*****************************************************************************
//
//! Configure the audio clock generation
//
//*****************************************************************************
void
PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
{
uint32_t ui32Reg;
uint32_t ui32MstDiv;
uint32_t ui32BitDiv;
uint32_t ui32WordDiv;
//
// Check the arguments.
//
ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) ||
(ui32SampleRate == I2S_SAMPLE_RATE_24K) ||
(ui32SampleRate == I2S_SAMPLE_RATE_32K) ||
(ui32SampleRate == I2S_SAMPLE_RATE_48K));
ui32MstDiv = 0;
ui32BitDiv = 0;
ui32WordDiv = 0;
//
// Make sure the audio clock generation is disabled before reconfiguring.
//
PRCMAudioClockDisable();
//
// Define the clock division factors for the audio interface.
//
switch(ui32SampleRate)
{
case I2S_SAMPLE_RATE_16K :
ui32MstDiv = 6;
ui32BitDiv = 60;
ui32WordDiv = 25;
break;
case I2S_SAMPLE_RATE_24K :
ui32MstDiv = 4;
ui32BitDiv = 40;
ui32WordDiv = 25;
break;
case I2S_SAMPLE_RATE_32K :
ui32MstDiv = 3;
ui32BitDiv = 30;
ui32WordDiv = 25;
break;
case I2S_SAMPLE_RATE_48K :
ui32MstDiv = 2;
ui32BitDiv = 20;
ui32WordDiv = 25;
break;
}
//
// Make sure to compensate the Frame clock division factor if using single
// phase format.
//
if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
{
ui32WordDiv -= 1;
}
//
// Write the clock divison factors.
//
HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
//
// Configure the Word clock format and polarity.
//
ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}
