int32_t psb_msvdx_alloc_fw_bo(struct drm_psb_private *dev_priv)
{
uint32_t core_rev;
int32_t ret = 0;
struct msvdx_private *msvdx_priv = dev_priv->msvdx_private;
core_rev = PSB_RMSVDX32(MSVDX_CORE_REV_OFFSET);
if ((core_rev & 0xffffff) < 0x020000)
msvdx_priv->mtx_mem_size = 16 * 1024;
else
msvdx_priv->mtx_mem_size = 56 * 1024;
PSB_DEBUG_INIT("MSVDX: MTX mem size is 0x%08x bytes, allocate firmware BO size 0x%08x\n", msvdx_priv->mtx_mem_size,
msvdx_priv->mtx_mem_size + 4096);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
ret = ttm_buffer_object_create(&dev_priv->bdev, msvdx_priv->mtx_mem_size + 4096, /* DMA may run over a page */
ttm_bo_type_kernel,
DRM_PSB_FLAG_MEM_MMU | TTM_PL_FLAG_NO_EVICT,
0, 0, 0, NULL, &msvdx_priv->fw);
#else
ret = ttm_buffer_object_create(&dev_priv->bdev, msvdx_priv->mtx_mem_size + 4096, /* DMA may run over a page */
ttm_bo_type_kernel,
DRM_PSB_FLAG_MEM_MMU | TTM_PL_FLAG_NO_EVICT,
0, 0, NULL, &msvdx_priv->fw);
#endif
if (ret) {
DRM_ERROR("MSVDX: allocate firmware BO fail\n");
}
return ret;
}
irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
{
struct drm_device *dev = (struct drm_device *)arg;
struct drm_psb_private *dev_priv =
(struct drm_psb_private *)dev->dev_private;
uint32_t vdc_stat;
uint32_t sgx_stat;
uint32_t sgx_stat2;
uint32_t msvdx_stat;
int handled = 0;
spin_lock(&dev_priv->irqmask_lock);
vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
sgx_stat = PSB_RSGX32(PSB_CR_EVENT_STATUS);
sgx_stat2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
msvdx_stat = PSB_RMSVDX32(MSVDX_INTERRUPT_STATUS);
sgx_stat2 &= dev_priv->sgx2_irq_mask;
sgx_stat &= dev_priv->sgx_irq_mask;
PSB_WSGX32(sgx_stat2, PSB_CR_EVENT_HOST_CLEAR2);
PSB_WSGX32(sgx_stat, PSB_CR_EVENT_HOST_CLEAR);
(void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR);
vdc_stat &= dev_priv->vdc_irq_mask;
spin_unlock(&dev_priv->irqmask_lock);
if (msvdx_stat) {
psb_msvdx_interrupt(dev, msvdx_stat);
handled = 1;
}
if (vdc_stat) {
#ifdef PSB_DETEAR
if(psb_blit_info.cmd_ready) {
psb_blit_info.cmd_ready = 0;
psb_blit_2d_reg_write(dev_priv, psb_blit_info.cmdbuf);
/* to resume the blocked psb_cmdbuf_2d() */
set_bit(0, &psb_blit_info.vdc_bit);
}
#endif /* PSB_DETEAR */
/* MSVDX IRQ status is part of vdc_irq_mask */
psb_vdc_interrupt(dev, vdc_stat);
handled = 1;
}
if (sgx_stat || sgx_stat2) {
psb_sgx_interrupt(dev, sgx_stat, sgx_stat2);
handled = 1;
}
if (!handled) {
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static void msvdx_get_mtx_control_from_dash(struct drm_psb_private *dev_priv)
{
struct msvdx_private *msvdx_priv = dev_priv->msvdx_private;
int count = 0;
uint32_t reg_val = 0;
REGIO_WRITE_FIELD(reg_val, MSVDX_MTX_DEBUG, MTX_DBG_IS_SLAVE, 1);
REGIO_WRITE_FIELD(reg_val, MSVDX_MTX_DEBUG, MTX_DBG_GPIO_IN, 0x02);
PSB_WMSVDX32(reg_val, MSVDX_MTX_DEBUG_OFFSET);
do {
reg_val = PSB_RMSVDX32(MSVDX_MTX_DEBUG_OFFSET);
count++;
} while (((reg_val & 0x18) != 0) && count < 50000);
if (count >= 50000)
PSB_DEBUG_GENERAL("MAVDX: timeout in get_mtx_control_from_dash\n");
/* Save the access control register...*/
msvdx_priv->psb_dash_access_ctrl = PSB_RMSVDX32(MTX_RAM_ACCESS_CONTROL_OFFSET);
}
/*
* MSVDX interrupt.
*/
static void psb_msvdx_interrupt(struct drm_device *dev, uint32_t msvdx_stat)
{
struct drm_psb_private *dev_priv =
(struct drm_psb_private *)dev->dev_private;
if (msvdx_stat & MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK) {
/*Ideally we should we should never get to this */
PSB_DEBUG_GENERAL
("******MSVDX: msvdx_stat: 0x%x fence2_irq_on=%d ***** (MMU FAULT)\n",
msvdx_stat, dev_priv->fence2_irq_on);
/* Pause MMU */
PSB_WMSVDX32(MSVDX_MMU_CONTROL0_CR_MMU_PAUSE_MASK,
MSVDX_MMU_CONTROL0);
DRM_WRITEMEMORYBARRIER();
/* Clear this interupt bit only */
PSB_WMSVDX32(MSVDX_INTERRUPT_STATUS_CR_MMU_FAULT_IRQ_MASK,
MSVDX_INTERRUPT_CLEAR);
PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR);
DRM_READMEMORYBARRIER();
dev_priv->msvdx_needs_reset = 1;
} else if (msvdx_stat & MSVDX_INTERRUPT_STATUS_CR_MTX_IRQ_MASK) {
PSB_DEBUG_GENERAL
("******MSVDX: msvdx_stat: 0x%x fence2_irq_on=%d ***** (MTX)\n",
msvdx_stat, dev_priv->fence2_irq_on);
/* Clear all interupt bits */
PSB_WMSVDX32(0xffff, MSVDX_INTERRUPT_CLEAR);
PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR);
DRM_READMEMORYBARRIER();
psb_msvdx_mtx_interrupt(dev);
}
}
void
psb_upload_fw (struct drm_psb_private *dev_priv, const uint32_t ui32DataMem,
uint32_t ui32RamBankSize, uint32_t ui32Address,
const unsigned int uiWords, const uint32_t * const pui32Data)
{
uint32_t ui32Loop, ui32Ctrl, ui32RamId, ui32Addr, ui32CurrBank =
(uint32_t) ~ 0;
uint32_t ui32AccessControl;
/* Save the access control register... */
ui32AccessControl = PSB_RMSVDX32 (MSVDX_MTX_RAM_ACCESS_CONTROL);
/* Wait for MCMSTAT to become be idle 1 */
psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
0xffffffff /* Enables */ );
for (ui32Loop = 0; ui32Loop < uiWords; ui32Loop++)
{
ui32RamId = ui32DataMem + (ui32Address / ui32RamBankSize);
if (ui32RamId != ui32CurrBank)
{
ui32Addr = ui32Address >> 2;
ui32Ctrl = 0;
REGIO_WRITE_FIELD_LITE (ui32Ctrl,
MSVDX_MTX_RAM_ACCESS_CONTROL,
MTX_MCMID, ui32RamId);
REGIO_WRITE_FIELD_LITE (ui32Ctrl,
MSVDX_MTX_RAM_ACCESS_CONTROL,
MTX_MCM_ADDR, ui32Addr);
REGIO_WRITE_FIELD_LITE (ui32Ctrl,
MSVDX_MTX_RAM_ACCESS_CONTROL, MTX_MCMAI, 1);
PSB_WMSVDX32 (ui32Ctrl, MSVDX_MTX_RAM_ACCESS_CONTROL);
ui32CurrBank = ui32RamId;
}
ui32Address += 4;
PSB_WMSVDX32 (pui32Data[ui32Loop], MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
/* Wait for MCMSTAT to become be idle 1 */
psb_wait_for_register (dev_priv, MSVDX_MTX_RAM_ACCESS_STATUS, 1, /* Required Value */
0xffffffff /* Enables */ );
}
static void msvdx_upload_fw(struct drm_psb_private *dev_priv,
const uint32_t data_mem, uint32_t ram_bank_size,
uint32_t address, const unsigned int words,
const uint32_t * const data)
{
uint32_t loop, ctrl, ram_id, addr, cur_bank = (uint32_t) ~0;
uint32_t access_ctrl;
PSB_DEBUG_GENERAL("MSVDX: Upload firmware by register interface\n");
/* Save the access control register... */
access_ctrl = PSB_RMSVDX32(MTX_RAM_ACCESS_CONTROL_OFFSET);
/* Wait for MCMSTAT to become be idle 1 */
psb_wait_for_register(dev_priv, MTX_RAM_ACCESS_STATUS_OFFSET,
1, /* Required Value */
0xffffffff, /* Enables */
2000000, 5);
for (loop = 0; loop < words; loop++) {
ram_id = data_mem + (address / ram_bank_size);
if (ram_id != cur_bank) {
addr = address >> 2;
ctrl = 0;
REGIO_WRITE_FIELD_LITE(ctrl,
MTX_RAM_ACCESS_CONTROL,
MTX_MCMID, ram_id);
REGIO_WRITE_FIELD_LITE(ctrl,
MTX_RAM_ACCESS_CONTROL,
MTX_MCM_ADDR, addr);
REGIO_WRITE_FIELD_LITE(ctrl,
MTX_RAM_ACCESS_CONTROL,
MTX_MCMAI, 1);
PSB_WMSVDX32(ctrl, MTX_RAM_ACCESS_CONTROL_OFFSET);
cur_bank = ram_id;
}
address += 4;
PSB_WMSVDX32(data[loop],
MTX_RAM_ACCESS_DATA_TRANSFER_OFFSET);
/* Wait for MCMSTAT to become be idle 1 */
psb_wait_for_register(dev_priv, MTX_RAM_ACCESS_STATUS_OFFSET,
1, /* Required Value */
0xffffffff, /* Enables */
2000000, 5);
}
/*
* the original 1000 of udelay is derive from reference driver
* From Liu, Haiyang, changed the originial udelay value from 1000 to 5
* can save 3% C0 residence
*/
int psb_wait_for_register(struct drm_psb_private *dev_priv,
uint32_t offset, uint32_t value, uint32_t enable)
{
uint32_t reg_value;
uint32_t poll_cnt = 2000000;
while (poll_cnt) {
reg_value = PSB_RMSVDX32(offset);
if (value == (reg_value & enable)) /* All the bits are reset */
return 0; /* So exit */
/* Wait a bit */
PSB_UDELAY(5);
poll_cnt--;
}
DRM_ERROR("MSVDX: Timeout while waiting for register %08x:"
" expecting %08x (mask %08x), got %08x\n",
offset, value, enable, reg_value);
return 1;
}
int
psb_wait_for_register (struct drm_psb_private *dev_priv,
uint32_t ui32Offset,
uint32_t ui32Value, uint32_t ui32Enable)
{
uint32_t ui32Temp;
uint32_t ui32PollCount = 1000;
while (ui32PollCount)
{
ui32Temp = PSB_RMSVDX32 (ui32Offset);
if (ui32Value == (ui32Temp & ui32Enable)) /* All the bits are reset */
return 0; /* So exit */
/* Wait a bit */
DRM_UDELAY (100);
ui32PollCount--;
}
PSB_DEBUG_GENERAL
("MSVDX: Timeout while waiting for register %08x: expecting %08x (mask %08x), got %08x\n",
ui32Offset, ui32Value, ui32Enable, ui32Temp);
return 1;
}
static void msvdx_upload_fw(struct drm_psb_private *dev_priv,
uint32_t address, const unsigned int words, int fw_sel)
{
uint32_t reg_val = 0;
uint32_t cmd;
uint32_t uCountReg, offset, mmu_ptd;
uint32_t size = (words * 4); /* byte count */
uint32_t dma_channel = 0; /* Setup a Simple DMA for Ch0 */
struct msvdx_private *msvdx_priv = dev_priv->msvdx_private;
PSB_DEBUG_GENERAL("MSVDX: Upload firmware by DMA\n");
msvdx_get_mtx_control_from_dash(dev_priv);
/* dma transfers to/from the mtx have to be 32-bit aligned and in multiples of 32 bits */
PSB_WMSVDX32(address, MTX_SYSC_CDMAA_OFFSET);
REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, BURSTSIZE, 4); /* burst size in multiples of 64 bits (allowed values are 2 or 4) */
REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, RNW, 0); /* false means write to mtx mem, true means read from mtx mem */
REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, ENABLE, 1); /* begin transfer */
REGIO_WRITE_FIELD_LITE(reg_val, MTX_SYSC_CDMAC, LENGTH, words); /* This specifies the transfer size of the DMA operation in terms of 32-bit words */
PSB_WMSVDX32(reg_val, MTX_SYSC_CDMAC_OFFSET);
/* toggle channel 0 usage between mtx and other msvdx peripherals */
{
reg_val = PSB_RMSVDX32(MSVDX_CONTROL_OFFSET);
REGIO_WRITE_FIELD(reg_val, MSVDX_CONTROL, DMAC_CH0_SELECT, 0);
PSB_WMSVDX32(reg_val, MSVDX_CONTROL_OFFSET);
}
/* Clear the DMAC Stats */
PSB_WMSVDX32(0 , DMAC_DMAC_IRQ_STAT_OFFSET + dma_channel);
offset = msvdx_priv->fw->offset;
if (fw_sel)
offset += ((msvdx_priv->mtx_mem_size + 8192) & ~0xfff);
/* use bank 0 */
cmd = 0;
PSB_WMSVDX32(cmd, MSVDX_MMU_BANK_INDEX_OFFSET);
/* Write PTD to mmu base 0*/
mmu_ptd = psb_get_default_pd_addr(dev_priv->mmu);
PSB_WMSVDX32(mmu_ptd, MSVDX_MMU_DIR_LIST_BASE_OFFSET + 0);
/* Invalidate */
reg_val = PSB_RMSVDX32(MSVDX_MMU_CONTROL0_OFFSET);
reg_val &= ~0xf;
REGIO_WRITE_FIELD(reg_val, MSVDX_MMU_CONTROL0, MMU_INVALDC, 1);
PSB_WMSVDX32(reg_val, MSVDX_MMU_CONTROL0_OFFSET);
PSB_WMSVDX32(offset, DMAC_DMAC_SETUP_OFFSET + dma_channel);
/* Only use a single dma - assert that this is valid */
if ((size / 4) >= (1 << 15)) {
DRM_ERROR("psb: DMA size beyond limited, aboart firmware uploading\n");
return;
}
uCountReg = PSB_DMAC_VALUE_COUNT(PSB_DMAC_BSWAP_NO_SWAP,
0, /* 32 bits */
PSB_DMAC_DIR_MEM_TO_PERIPH,
0,
(size / 4));
/* Set the number of bytes to dma*/
PSB_WMSVDX32(uCountReg, DMAC_DMAC_COUNT_OFFSET + dma_channel);
cmd = PSB_DMAC_VALUE_PERIPH_PARAM(PSB_DMAC_ACC_DEL_0, PSB_DMAC_INCR_OFF, PSB_DMAC_BURST_2);
PSB_WMSVDX32(cmd, DMAC_DMAC_PERIPH_OFFSET + dma_channel);
/* Set destination port for dma */
cmd = 0;
REGIO_WRITE_FIELD(cmd, DMAC_DMAC_PERIPHERAL_ADDR, ADDR, MTX_SYSC_CDMAT_OFFSET);
PSB_WMSVDX32(cmd, DMAC_DMAC_PERIPHERAL_ADDR_OFFSET + dma_channel);
/* Finally, rewrite the count register with the enable bit set*/
PSB_WMSVDX32(uCountReg | DMAC_DMAC_COUNT_EN_MASK, DMAC_DMAC_COUNT_OFFSET + dma_channel);
/* Wait for all to be done */
if (psb_wait_for_register(dev_priv,
DMAC_DMAC_IRQ_STAT_OFFSET + dma_channel,
DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_MASK,
DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_MASK,
2000000, 5)) {
psb_setup_fw_dump(dev_priv, dma_channel);
msvdx_release_mtx_control_from_dash(dev_priv);
return;
}
/* Assert that the MTX DMA port is all done aswell */
if (psb_wait_for_register(dev_priv,
MTX_SYSC_CDMAS0_OFFSET,
1, 1, 2000000, 5)) {
msvdx_release_mtx_control_from_dash(dev_priv);
return;
}
msvdx_release_mtx_control_from_dash(dev_priv);
PSB_DEBUG_GENERAL("MSVDX: Upload done\n");
}
/* for future debug info of msvdx related registers */
static void psb_setup_fw_dump(struct drm_psb_private *dev_priv, uint32_t dma_channel)
{
/* for DMAC REGISTER */
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_CDMAA is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_CDMAA_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_CDMAC value is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_CDMAC_OFFSET));
DRM_ERROR("MSVDX: Upload firmware DMAC_SETUP value is 0x%x\n", PSB_RMSVDX32(DMAC_DMAC_SETUP_OFFSET + dma_channel));
DRM_ERROR("MSVDX: Upload firmware DMAC_DMAC_COUNT value is 0x%x\n", PSB_RMSVDX32(DMAC_DMAC_COUNT_OFFSET + dma_channel));
DRM_ERROR("MSVDX: Upload firmware DMAC_DMAC_PERIPH_OFFSET value is 0x%x\n", PSB_RMSVDX32(DMAC_DMAC_PERIPH_OFFSET + dma_channel));
DRM_ERROR("MSVDX: Upload firmware DMAC_DMAC_PERIPHERAL_ADDR value is 0x%x\n", PSB_RMSVDX32(DMAC_DMAC_PERIPHERAL_ADDR_OFFSET + dma_channel));
DRM_ERROR("MSVDX: Upload firmware MSVDX_CONTROL value is 0x%x\n", PSB_RMSVDX32(MSVDX_CONTROL_OFFSET));
DRM_ERROR("MSVDX: Upload firmware DMAC_DMAC_IRQ_STAT value is 0x%x\n", PSB_RMSVDX32(DMAC_DMAC_IRQ_STAT_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_MMU_CONTROL0 value is 0x%x\n", PSB_RMSVDX32(MSVDX_MMU_CONTROL0_OFFSET));
DRM_ERROR("MSVDX: Upload firmware DMAC_DMAC_COUNT 2222 value is 0x%x\n", PSB_RMSVDX32(DMAC_DMAC_COUNT_OFFSET + dma_channel));
/* for MTX REGISTER */
DRM_ERROR("MSVDX: Upload firmware MTX_ENABLE_OFFSET is 0x%x\n", PSB_RMSVDX32(MTX_ENABLE_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_KICK_INPUT_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_KICK_INPUT_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_REGISTER_READ_WRITE_REQUEST_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_REGISTER_READ_WRITE_REQUEST_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_RAM_ACCESS_CONTROL_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_RAM_ACCESS_CONTROL_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_RAM_ACCESS_STATUS_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_RAM_ACCESS_STATUS_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_TIMERDIV_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_TIMERDIV_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_CDMAC_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_CDMAC_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_CDMAA_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_CDMAA_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_CDMAS0_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_CDMAS0_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MTX_SYSC_CDMAT_OFFSET value is 0x%x\n", PSB_RMSVDX32(MTX_SYSC_CDMAT_OFFSET));
/* for MSVDX CORE REGISTER */
DRM_ERROR("MSVDX: Upload firmware MSVDX_CONTROL_OFFSET is 0x%x\n", PSB_RMSVDX32(MSVDX_CONTROL_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_INTERRUPT_CLEAR_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_INTERRUPT_CLEAR_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_INTERRUPT_STATUS_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_INTERRUPT_STATUS_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_HOST_INTERRUPT_ENABLE_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_HOST_INTERRUPT_ENABLE_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_MAN_CLK_ENABLE_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_MAN_CLK_ENABLE_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_CORE_ID_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_CORE_ID_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_MMU_STATUS_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_MMU_STATUS_OFFSET));
DRM_ERROR("MSVDX: Upload firmware FE_MSVDX_WDT_CONTROL_OFFSET value is 0x%x\n", PSB_RMSVDX32(FE_MSVDX_WDT_CONTROL_OFFSET));
DRM_ERROR("MSVDX: Upload firmware FE_MSVDX_WDTIMER_OFFSET value is 0x%x\n", PSB_RMSVDX32(FE_MSVDX_WDTIMER_OFFSET));
DRM_ERROR("MSVDX: Upload firmware BE_MSVDX_WDT_CONTROL_OFFSET value is 0x%x\n", PSB_RMSVDX32(BE_MSVDX_WDT_CONTROL_OFFSET));
DRM_ERROR("MSVDX: Upload firmware BE_MSVDX_WDTIMER_OFFSET value is 0x%x\n", PSB_RMSVDX32(BE_MSVDX_WDTIMER_OFFSET));
/* for MSVDX RENDEC REGISTER */
DRM_ERROR("MSVDX: Upload firmware VEC_SHIFTREG_CONTROL_OFFSET is 0x%x\n", PSB_RMSVDX32(VEC_SHIFTREG_CONTROL_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_CONTROL0_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_CONTROL0_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_BUFFER_SIZE_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_BUFFER_SIZE_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_BASE_ADDR0_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_BASE_ADDR0_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_BASE_ADDR1_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_BASE_ADDR1_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_READ_DATA_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_READ_DATA_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_CONTEXT0_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_CONTEXT0_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_RENDEC_CONTEXT1_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_RENDEC_CONTEXT1_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_CMDS_END_SLICE_PICTURE_OFFSET value is 0x%x\n", PSB_RMSVDX32(MSVDX_CMDS_END_SLICE_PICTURE_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_MMU_MEM_REQ value is 0x%x\n", PSB_RMSVDX32(MSVDX_MMU_MEM_REQ_OFFSET));
DRM_ERROR("MSVDX: Upload firmware MSVDX_SYS_MEMORY_DEBUG2 value is 0x%x\n", PSB_RMSVDX32(0x6fc));
}