/** Reads a 32-bit PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume. Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. @return The 32-bit PCI configuration register specified by Address. **/ UINT32 EFIAPI S3PciSegmentRead32 ( IN UINT64 Address ) { return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address)); }
/** Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register. @param AndData The value to AND with the PCI configuration register. @return The value written back to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentAnd32 ( IN UINT64 Address, IN UINT32 AndData ) { return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); }
/** Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register. @param OrData The value to OR with the PCI configuration register. @return The value written back to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentOr32 ( IN UINT64 Address, IN UINT32 OrData ) { return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); }
/** Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value. Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register. @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. @return The value written back to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentAndThenOr32 ( IN UINT64 Address, IN UINT32 AndData, IN UINT32 OrData ) { return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); }
/** Reads a bit field of a PCI configuration register. Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned. If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @param Address PCI configuration register to read. @param StartBit The ordinal of the least significant bit in the bit field. Range 0..31. @param EndBit The ordinal of the most significant bit in the bit field. Range 0..31. @return The value of the bit field read from the PCI configuration register. **/ UINT32 EFIAPI PciSegmentBitFieldRead32 ( IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit ) { return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); }
/** Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register. Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped. If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @param Address PCI configuration register to write. @param StartBit The ordinal of the least significant bit in the bit field. Range 0..31. @param EndBit The ordinal of the most significant bit in the bit field. Range 0..31. @param AndData The value to AND with the PCI configuration register. @return The value written back to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentBitFieldAnd32 ( IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData ) { return PciSegmentWrite32 ( Address, BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData) ); }
/** Writes a bit field to a PCI configuration register. Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned. If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @param Address PCI configuration register to write. @param StartBit The ordinal of the least significant bit in the bit field. Range 0..31. @param EndBit The ordinal of the most significant bit in the bit field. Range 0..31. @param Value New value of the bit field. @return The value written back to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentBitFieldWrite32 ( IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value ) { return PciSegmentWrite32 ( Address, BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value) ); }
/** Reads a range of PCI configuration registers into a caller supplied buffer. Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range. If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT(). @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device, Function and Register. @param Size Size in bytes of the transfer. @param Buffer Pointer to a buffer receiving the data read. @return Size **/ UINTN EFIAPI PciSegmentReadBuffer ( IN UINT64 StartAddress, IN UINTN Size, OUT VOID *Buffer ) { UINTN ReturnValue; ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); if (Size == 0) { return Size; } ASSERT (Buffer != NULL); // // Save Size for return // ReturnValue = Size; if ((StartAddress & 1) != 0) { // // Read a byte if StartAddress is byte aligned // *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); StartAddress += sizeof (UINT8); Size -= sizeof (UINT8); Buffer = (UINT8*)Buffer + 1; } if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { // // Read a word if StartAddress is word aligned // *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress); StartAddress += sizeof (UINT16); Size -= sizeof (UINT16); Buffer = (UINT16*)Buffer + 1; } while (Size >= sizeof (UINT32)) { // // Read as many double words as possible // *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress); StartAddress += sizeof (UINT32); Size -= sizeof (UINT32); Buffer = (UINT32*)Buffer + 1; } if (Size >= sizeof (UINT16)) { // // Read the last remaining word if exist // *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress); StartAddress += sizeof (UINT16); Size -= sizeof (UINT16); Buffer = (UINT16*)Buffer + 1; } if (Size >= sizeof (UINT8)) { // // Read the last remaining byte if exist // *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); } return ReturnValue; }