/**
* Various initialization needed prior topology and configuration initialization
*
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PcieFmPreInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 Index;
PCIe_SILICON_CONFIG *Silicon;
PCIE_LINK_SPEED_CAP GlobalCapability;
F14_PCIe_WRAPPER_CONFIG *F14PcieWrapper;
Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
F14PcieWrapper = &((F14_COMPLEX_CONFIG*) Silicon)->FmGppWrapper ;
GlobalCapability = PcieUtilGlobalGenCapability (
PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_ALL_PORTS,
Pcie
);
if ((GlobalCapability == PcieGen1) && (F14PcieWrapper->NativeGen1Support == TRUE)) {
PcieFmExecuteNativeGen1Reconfig (Pcie);
}
Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) {
PcieSiliconRegisterRMW (
Silicon,
PcieInitTable[Index].Reg,
PcieInitTable[Index].Mask,
PcieInitTable[Index].Data,
FALSE,
Pcie
);
}
// Set PCIe SSID.
PcieSiliconRegisterRMW (
Silicon,
WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS),
D0F0xE4_WRAP_8002_SubsystemVendorID_MASK | D0F0xE4_WRAP_8002_SubsystemID_MASK,
UserOptions.CfgGnbPcieSSID,
FALSE,
Pcie
);
}
/**
* Control port visibility in PCI config space
*
*
* @param[in] Control Make port Hide/Unhide ports
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PciePortsVisibilityControl (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_COMPLEX_CONFIG *ComplexList;
ComplexList = &Pcie->ComplexList[0];
while (ComplexList != NULL) {
PCIe_SILICON_CONFIG *SiliconList;
SiliconList = PcieComplexGetSiliconList (ComplexList);
while (SiliconList != NULL) {
PcieFmPortVisabilityControl (Control, SiliconList, Pcie);
SiliconList = PcieLibGetNextDescriptor (SiliconList);
}
ComplexList = PcieLibGetNextDescriptor (ComplexList);
}
}
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN PCIe_COMPLEX_CONFIG *Complex,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *Silicon;
PCIe_WRAPPER_CONFIG *Wrapper;
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
GNB_DEBUG_CODE (
PcieComplexConfigConfigDump (ComplexDescriptor, Pcie);
);
Silicon = PcieComplexGetSiliconList (Complex);
while (Silicon != NULL) {
Wrapper = PcieSiliconGetWrapperList (Silicon);
while (Wrapper != NULL) {
Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n",
PcieFmDebugGetWrapperNameString (Wrapper)
);
ASSERT (FALSE);
}
Wrapper = PcieLibGetNextDescriptor (Wrapper);
}
Status = PcieMapPortsPciAddresses (Silicon, Pcie);