UINT32
STATIC
PcieUtilGetDdiEngineLaneBitMap (
IN LANE_TYPE LaneType,
IN LANE_PROPERTY LaneProperty,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
UINT8 Width;
UINT16 Offset;
Width = 0;
Offset = 0;
LaneBitmap = 0;
if (PcieConfigIsDdiEngine (Engine)) {
if (PcieConfigIsEngineAllocated (Engine)) {
if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
LaneBitmap = ((1 << Width) - 1) << Offset;
}
if (LaneType == LaneTypeNativePhy) {
LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
}
}
}
return LaneBitmap;
}
/**
* Get max link speed capability supported by this port
*
*
*
* @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
* @param[in] Engine Pointer to engine config descriptor
* @retval PcieGen1/PcieGen2 Max supported link gen capability
*/
PCIE_LINK_SPEED_CAP
PcieGetLinkSpeedCapML (
IN UINT32 Flags,
IN PCIe_ENGINE_CONFIG *Engine
)
{
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
PCIe_WRAPPER_CONFIG *Wrapper;
PCIe_PLATFORM_CONFIG *Pcie;
Wrapper = PcieConfigGetParentWrapper (Engine);
Pcie = PcieConfigGetPlatform (Wrapper);
LinkSpeedCapability = PcieGen2;
if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) {
Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability;
}
if (Pcie->PsppPolicy == PsppPowerSaving) {
LinkSpeedCapability = PcieGen1;
}
if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) {
LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
}
if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
if (( Pcie->PsppPolicy == PsppBalanceLow ||
Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1)
&& !PcieConfigIsSbPcieEngine (Engine)) {
LinkSpeedCapability = PcieGen1;
}
}
return LinkSpeedCapability;
}
BOOLEAN
PcieCheckPortPcieLaneCanBeMuxedML (
IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT16 DescriptorHiLane;
UINT16 DescriptorLoLane;
UINT16 DescriptorNumberOfLanes;
PCIe_WRAPPER_CONFIG *Wrapper;
UINT16 NormalizedLoPhyLane;
BOOLEAN Result;
Result = FALSE;
Wrapper = PcieConfigGetParentWrapper (Engine);
DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane;
if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) {
Result = TRUE;
} else {
if (NormalizedLoPhyLane == 0) {
Result = TRUE;
} else {
if ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0) {
Result = TRUE;
}
}
}
return Result;
}
UINT32
STATIC
PcieUtilGetPcieEngineLaneBitMap (
IN LANE_TYPE LaneType,
IN LANE_PROPERTY LaneProperty,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
UINT8 Width;
UINT16 Offset;
UINT16 LoPhylane;
UINT16 HiPhylane;
PCIe_PLATFORM_CONFIG *Pcie;
Width = 0;
Offset = 0;
LaneBitmap = 0;
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
if (PcieConfigIsPcieEngine (Engine)) {
if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) {
Width = PcieConfigGetNumberOfCoreLane (Engine);
Offset = Engine->Type.Port.StartCoreLane;
LaneBitmap = ((1 << Width) - 1) << Offset;
} else if (PcieConfigIsEngineAllocated (Engine)) {
if (LaneType == LaneTypeNativePhy) {
LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
} else {
if (LaneType == LaneTypeCore) {
if (LaneProperty == LanePropertyActive) {
Width = PcieUtilGetLinkWidth (Engine, Pcie);
Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
} else if (LaneProperty == LanePropertyAllocated) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
}
}
if (LaneType == LaneTypePhy) {
LoPhylane = PcieLibGetLoPhyLane (Engine);
HiPhylane = PcieLibGetHiPhyLane (Engine);
if (LaneProperty == LanePropertyActive) {
Width = PcieUtilGetLinkWidth (Engine, Pcie);
Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
} else if (LaneProperty == LanePropertyAllocated) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
}
}
LaneBitmap = ((1 << Width) - 1) << Offset;
}
}
}
return LaneBitmap;
}
/**
* PCie EP not present
*
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingNotPresent (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) {
} else {
PcieRegisterWriteField (
PcieConfigGetParentWrapper (CurrentEngine),
WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
1,
FALSE,
Pcie
);
}
PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
}
/**
* Release training
*
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingRelease (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 LinkTrainingState;
PcieRegisterWriteField (
PcieConfigGetParentWrapper (CurrentEngine),
WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
0,
FALSE,
Pcie
);
if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
LinkTrainingState = LinkStateCompliance;
} else {
LinkTrainingState = LinkStateDetectPresence;
}
PcieTrainingSetPortStateV2 (CurrentEngine, LinkTrainingState, TRUE, Pcie);
}
/**
* get Master Lane of PCIe port engine
*
*
*
* @param[in] Engine Pointer to engine descriptor
* @retval Master Engine Lane Number
*/
UINT8
PcieConfigGetPcieEngineMasterLane (
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT8 MasterLane;
PCIe_WRAPPER_CONFIG *Wrapper;
ASSERT (PcieConfigIsPcieEngine (Engine));
Wrapper = PcieConfigGetParentWrapper (Engine);
if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) {
MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane);
} else {
MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane);
}
return MasterLane;
}
VOID
STATIC
PcieMidPortCharacterizationCallbackKV (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SUBLINK_INFO *SublinkInfo;
PCIe_WRAPPER_INFO *WrapperInfo;
PCIe_ASPM_LATENCY_INFO LinkLatencyInfo;
DxFxxE4_xA4_STRUCT DxFxxE4_xA4;
SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]);
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[PcieConfigGetParentWrapper (Engine)->WrapId]);
LinkLatencyInfo.MaxL1ExitLatency = 255;
LinkLatencyInfo.MaxL0sExitLatency = 255;
// Count x1/x2 GPP port on each sublink
if (ABS (Engine->EngineData.StartLane - Engine->EngineData.EndLane) <= 2) {
SublinkInfo->GppPortCount += 1;
}
// Determine max gen capability of this engine and sublink
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
// Port is trained, use device capability
DxFxxE4_xA4.Value = PciePortRegisterRead (Engine, DxFxxE4_xA4_ADDRESS, Pcie);
if (DxFxxE4_xA4.Field.LcOtherSideSupportsGen2 == 1) {
SublinkInfo->MaxGenCapability = Gen2;
}
// Determine minimum L1 exit latency for this engine
PcieAspmGetMinExitLatencyV5 (Engine->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
if (LinkLatencyInfo.MaxL1ExitLatency < WrapperInfo->MinAspmL1ExitLatency) {
WrapperInfo->MinAspmL1ExitLatency = LinkLatencyInfo.MaxL1ExitLatency;
}
} else {
// Hotplug port - use max supported speed
if (Engine->Type.Port.PortData.LinkSpeedCapability > SublinkInfo->MaxGenCapability) {
SublinkInfo->MaxGenCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
}
}
}
/**
* Reduce link width
*
*
* @param[in] LinkWidth Link width
* @param[in] Engine Pointer to Engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyReduceLinkWidth (
IN UINT8 LinkWidth,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
UINT32 LinkReversed;
UINT8 DeltaLinkWidthBitmap;
UINT32 LanesToDisable;
Wrapper = PcieConfigGetParentWrapper (Engine);
LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth)));
PcieTopologyLaneControl (
DisableLanes,
LanesToDisable,
Wrapper,
Pcie
);
}
AGESA_STATUS
PcieFmMapPortPciAddress (
IN PCIe_ENGINE_CONFIG *Engine
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
PCIe_PLATFORM_CONFIG *Pcie;
UINT64 ConfigurationSignature;
Wrapper = PcieConfigGetParentWrapper (Engine);
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
if (Wrapper->WrapId == GPP_WRAP_ID) {
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId);
if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) {
//Enable device remapping
GnbLibPciIndirectRMW (
MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
D0F0x64_x20_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32) (1 << D0F0x64_x20_IocPcieDevRemapDis_OFFSET),
0x0,
GnbLibGetHeader (Pcie)
);
}
}
if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
return AGESA_SUCCESS;
}
if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) {
return AGESA_SUCCESS;
}
return AGESA_ERROR;
}
VOID
STATIC
PcieMidPortInitCallbackKV (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxx68_STRUCT DxFxx68;
D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
PCIe_SUBLINK_INFO *SublinkInfo;
PCIe_WRAPPER_INFO *WrapperInfo;
PCIe_WRAPPER_CONFIG *Wrapper;
CPU_LOGICAL_ID LogicalId;
UINT8 Count;
UINT8 Nibble;
PciePortProgramRegisterTable (PortInitMidTableKV.Table, PortInitMidTableKV.Length, Engine, TRUE, Pcie);
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
PcieEnableSlotPowerLimitV5 (Engine, Pcie);
if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
PcieInitPortForIommuV4 (Engine, Pcie);
}
// After GFX link is trained up and before ASPM is enabled, AGESA needs to check link width,
// if it equals to x16, then apply the following change to GFX port:
// Per port register 0xA1 - PCIE LC TRAINING CONTROL, bit16 - LC_EXTEND_WAIT_FOR_SKP = 1
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS,
AccessWidth32,
&DxFxx68,
GnbLibGetHeader (Pcie)
);
if (DxFxx68.Field.NegotiatedLinkWidth == 16) {
PciePortRegisterRMW (
Engine,
DxFxxE4_xA1_ADDRESS,
DxFxxE4_xA1_LcExtendWaitForSkp_MASK,
(1 << DxFxxE4_xA1_LcExtendWaitForSkp_OFFSET),
TRUE,
Pcie
);
}
}
Wrapper = PcieConfigGetParentWrapper (Engine);
SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]);
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]);
GetLogicalIdOfCurrentCore (&LogicalId, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// Check if this CPU is KV A0
// UBTS468566
if ((LogicalId.Revision & AMD_F15_KV_A0) != 0) {
Count = SublinkInfo->GppPortCount;
IDS_HDT_CONSOLE (GNB_TRACE, "x1x2 PortCount = %02x\n", Count);
if (Count == 2) {
// If number of GPP ports under the same sublink is 2, Delay L1 Exit (prolong minimum time spent in L1)
PciePortRegisterRMW (
Engine,
DxFxxE4_xA0_ADDRESS,
DxFxxE4_xA0_LcDelayCount_MASK |
DxFxxE4_xA0_LcDelayL1Exit_MASK,
(0 << DxFxxE4_xA0_LcDelayCount_OFFSET) |
(1 << DxFxxE4_xA0_LcDelayL1Exit_OFFSET),
TRUE,
Pcie
);
} else if (Count > 2) {
// If number of GPP ports > 2
if (SublinkInfo->MaxGenCapability > Gen1) {
// If at least 1 GPP is Gen2 capable, Disable PLL Power down feature
Wrapper = PcieConfigGetParentWrapper (Engine);
Nibble = (UINT8) ((MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) % 8) / 4);
// Only PSD and PPD can have x1/x2 links, so we assume that PIF number is always 0
D0F0xE4_PIF_0012.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
Pcie
);
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
} else {
// All ports are only Gen1
PciePortRegisterRMW (
Engine,
DxFxxE4_xC0_ADDRESS,
DxFxxE4_xC0_StrapMedyTSxCount_MASK,
0x2 << DxFxxE4_xC0_StrapMedyTSxCount_OFFSET,
TRUE,
Pcie
);
}
}
}
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0802_ADDRESS + (0x100 * Engine->Type.Port.PortId)),
D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_MASK,
(WrapperInfo->L1ExitLatencyValue << D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_OFFSET),
TRUE,
Pcie
);
if (WrapperInfo->DisableL1OnWrapper == TRUE) {
Engine->Type.Port.PortData.LinkAspm &= ~(AspmL1);
}
PcieEnableAspm (Engine, Pcie);
}
/**
* Set current link speed
*
*
* @param[in] LinkSpeedCapability Link Speed Capability
* @param[in] Engine Pointer to engine configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PcieSetLinkSpeedCapV4 (
IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xA4_STRUCT DxF0xE4_xA4;
DxF0xE4_xC0_STRUCT DxF0xE4_xC0;
DxF0x88_STRUCT DxF0x88;
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
AccessWidth32,
&DxF0x88.Value,
GnbLibGetHeader (Pcie)
);
DxF0xE4_xA4.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xA4_ADDRESS,
Pcie
);
DxF0xE4_xC0.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xC0_ADDRESS,
Pcie
);
switch (LinkSpeedCapability) {
case PcieGen3:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
DxF0xE4_xA4.Field.LcGen3EnStrap = 0x1;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
DxF0x88.Field.TargetLinkSpeed = 0x3;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
PciePortRegisterRMW (
Engine,
DxF0xE4_xA2_ADDRESS,
DxF0xE4_xA2_LcDynLanesPwrState_MASK,
(2 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET),
FALSE,
Pcie
);
break;
case PcieGen2:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
DxF0x88.Field.TargetLinkSpeed = 0x2;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
break;
case PcieGen1:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
DxF0x88.Field.TargetLinkSpeed = 0x1;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
0,
FALSE,
Pcie
);
break;
default:
ASSERT (FALSE);
break;
}
if ((Pcie->PsppPolicy == PsppDisabled) || (PcieConfigIsSbPcieEngine (Engine))) {
DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
} else {
DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
}
PciePortRegisterWrite (
Engine,
DxF0xE4_xA4_ADDRESS,
DxF0xE4_xA4.Value,
FALSE,
Pcie
);
PciePortRegisterWrite (
Engine,
DxF0xE4_xC0_ADDRESS,
DxF0xE4_xC0.Value,
FALSE,
Pcie
);
GnbLibPciWrite (
Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
AccessWidth32,
&DxF0x88.Value,
GnbLibGetHeader (Pcie)
);
}
VOID
STATIC
PcieEarlyPortInitCallbackCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Enter\n");
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitEarlyTableCZ.Table, PortInitEarlyTableCZ.Length, Engine, FALSE, Pcie);
IDS_OPTION_HOOK (IDS_GNB_EQUAL_PRESET, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplugCZ (Engine, Pcie);
//Move EXTENDED_FMT_SUPPORTED stting from Mid to here.
PciePortRegisterRMW (
Engine,
DxFxxE4_xC1_ADDRESS,
DxFxxE4_xC1_StrapE2EPrefixEn_MASK | DxFxxE4_xC1_StrapExtendedFmtSupported_MASK,
(1 << DxFxxE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxFxxE4_xC1_StrapExtendedFmtSupported_OFFSET),
FALSE,
Pcie
);
if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
(Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
ASSERT (!PcieConfigIsSbPcieEngine (Engine));
//
// Pass endpoint status in scratch
//
PciePortRegisterRMW (
Engine,
DxFxxE4_x01_ADDRESS,
0x1,
0x1,
FALSE,
Pcie
);
PcieTrainingSetPortStateV2 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
if (PcieConfigIsSbPcieEngine (Engine)) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_001C_ADDRESS),
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_OFFSET,
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
IDS_OPTION_HOOK (IDS_GNB_GEN1_LOOPBACK, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Exit\n");
}
VOID
STATIC
PcieLinkInitHotplugCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxxE4_xB5_STRUCT DxFxxE4_xB5;
UINT32 Value;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxFxxE4_xB5.Value = PciePortRegisterRead (Engine, DxFxxE4_xB5_ADDRESS, Pcie);
DxFxxE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxFxxE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxFxxE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
DxFxxE4_xB5.Field.LcRcvrDetEnOverride = 0;
PciePortRegisterWrite (
Engine,
DxFxxE4_xB5_ADDRESS,
DxFxxE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0118_ADDRESS),
D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_OFFSET,
D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxFxx6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxFxx6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxFxxE4_x20_ADDRESS,
DxFxxE4_x20_TxFlushTlpDis_OFFSET,
DxFxxE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxFxxE4_x70_ADDRESS,
DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) {
Value = 1;
} else {
Value = 0;
}
PciePortRegisterWriteField (
Engine,
DxFxxE4_x10_ADDRESS,
DxFxxE4_x10_NativePmeEn_OFFSET,
DxFxxE4_x10_NativePmeEn_WIDTH,
Value,
TRUE,
Pcie
);
}
/**
* Get engine PHY lanes bitmap
*
*
*
* @param[in] Engine Pointer to engine config descriptor
*/
UINT32
PcieConfigGetEnginePhyLaneBitMap (
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitMap;
LaneBitMap = 0;
if (PcieLibIsEngineAllocated (Engine)) {
LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane);
}
return LaneBitMap;
}
VOID
PcieLinkInitHotplug (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xB5_STRUCT DxF0xE4_xB5;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
PciePortRegisterWrite (
Engine,
DxF0xE4_xB5_ADDRESS,
DxF0xE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET,
D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxF0x6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x20_ADDRESS,
DxF0xE4_x20_TxFlushTlpDis_OFFSET,
DxF0xE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x70_ADDRESS,
DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
}
