/** * Helper function to dump wrapper configuration * * * @param[in] WrapperList Wrapper Configuration */ VOID PcieConfigWrapperDebugDump ( IN PCIe_WRAPPER_CONFIG *WrapperList ) { PCIe_ENGINE_CONFIG *EngineList; IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", PcieFmDebugGetWrapperNameString (WrapperList) ); IDS_HDT_CONSOLE (PCIE_MISC, " Start PHY lane - %02d\n", WrapperList->StartPhyLane); IDS_HDT_CONSOLE (PCIE_MISC, " End PHY lane - %02d\n", WrapperList->EndPhyLane); IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags); IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n" " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n", WrapperList->Features.PowerOffUnusedLanes, WrapperList->Features.PowerOffUnusedPlls, WrapperList->Features.ClkGating, WrapperList->Features.LclkGating, WrapperList->Features.TxclkGatingPllPowerDown, WrapperList->Features.PllOffInL1 ); IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n", PcieFmDebugGetWrapperNameString (WrapperList) ); EngineList = PcieConfigGetChildEngine (WrapperList); while (EngineList != NULL) { if (PcieLibIsEngineAllocated (EngineList)) { PcieConfigEngineDebugDump (EngineList); } EngineList = PcieLibGetNextDescriptor (EngineList); } }
AGESA_STATUS STATIC PcieTopologySetCoreConfigCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, OUT BOOLEAN *ConfigChanged, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 CoreId; AGESA_STATUS Status; D0F0xE4_WRAP_0080_STRUCT D0F0xE4_WRAP_0080; Status = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Enter\n"); if (PcieLibIsPcieWrapper (Wrapper)) { for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { UINT64 ConfigurationSignature; UINT8 NewConfigurationValue; ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); if (Status == AGESA_SUCCESS) { D0F0xE4_WRAP_0080.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), Pcie ); IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s Original configuration - %s\n", PcieFmDebugGetWrapperNameString (Wrapper), CoreId, PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue), PcieFmDebugGetCoreConfigurationString (Wrapper, (UINT8) D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig) ); if (ConfigChanged != NULL) { if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) { *ConfigChanged = TRUE; } } D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), D0F0xE4_WRAP_0080.Value, FALSE, Pcie ); } else { IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", PcieFmDebugGetWrapperNameString (Wrapper), ((UINT32*)&ConfigurationSignature)[1], ((UINT32*)&ConfigurationSignature)[0] ); PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); } } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Exit\n"); return Status; }
AGESA_STATUS PcieTopologySetCoreConfig ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 CoreId; AGESA_STATUS Status; Status = AGESA_SUCCESS; if (PcieLibIsPcieWrapper (Wrapper)) { for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { UINT64 ConfigurationSignature; UINT8 NewConfigurationValue; ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); if (Status == AGESA_SUCCESS) { IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n", PcieFmDebugGetWrapperNameString (Wrapper), CoreId, PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue) ); PcieRegisterWriteField ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET, D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH, NewConfigurationValue, FALSE, Pcie ); } else { IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", PcieFmDebugGetWrapperNameString (Wrapper), ((UINT32*)&ConfigurationSignature)[1], ((UINT32*)&ConfigurationSignature)[0] ); PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); } } } return Status; }
AGESA_STATUS PcieMapTopologyOnComplex ( IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, IN PCIe_COMPLEX_CONFIG *Complex, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIe_SILICON_CONFIG *Silicon; PCIe_WRAPPER_CONFIG *Wrapper; AGESA_STATUS AgesaStatus; AGESA_STATUS Status; AgesaStatus = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n"); Silicon = PcieConfigGetChildSilicon (Complex); while (Silicon != NULL) { Wrapper = PcieConfigGetChildWrapper (Silicon); while (Wrapper != NULL) { Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_ERROR) { PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n", PcieFmDebugGetWrapperNameString (Wrapper) ); ASSERT (FALSE); } Wrapper = PcieLibGetNextDescriptor (Wrapper); } Status = PcieMapPortsPciAddresses (Silicon, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); Silicon = PcieLibGetNextDescriptor (Silicon); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus); return AgesaStatus; }