/** * Init core registers. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID STATIC PcieEarlyCoreInitCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 CoreId; UINTN Index; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitCZ Enter\n"); for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { for (Index = 0; Index < CoreInitTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, CORE_SPACE (CoreId, CoreInitTableCZ.Table[Index].Reg), Pcie ); Value &= (~CoreInitTableCZ.Table[Index].Mask); Value |= CoreInitTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, CORE_SPACE (CoreId, CoreInitTableCZ.Table[Index].Reg), Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitCZ Exit\n"); } }
/** * Set TX control for PCIe lanes * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieWrapSetTxS1CtrlForLaneMux ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025; UINT32 LaneBitmap; UINTN Index; D0F0xE4_WRAP_8025.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), Pcie ); Index = 0; LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); while (LaneBitmap != 0) { if ((LaneBitmap & 0xf) != 0) { D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8))); D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8)); } LaneBitmap >>= 4; ++Index; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), D0F0xE4_WRAP_8025.Value, FALSE, Pcie ); }
/** * Init SRBM reset * * @param[in] SrbmResetEnable SRBM reset enable flag. * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyInitSrbmReset ( IN BOOLEAN SrbmResetEnable, IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 pcireg; UINT32 regmask = 0x7030;; pcireg = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), Pcie ); if (SrbmResetEnable) { pcireg |= regmask; } else { pcireg &= ~(regmask); } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, 0x8063), pcireg, FALSE, Pcie ); }
/** * Common Core Init * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieCommonCoreInit ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 CoreId; UINTN Index; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, CORE_SPACE (CoreId, CoreInitTable[Index].Reg), Pcie ); Value &= (~CoreInitTable[Index].Mask); Value |= CoreInitTable[Index].Data; PcieRegisterWrite ( Wrapper, CORE_SPACE (CoreId, CoreInitTable[Index].Reg), Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n"); } }
/** * Lanes enable/disable control * * @param[in] Control Lane control action * @param[in] LaneBitMap Core lanes bitmap * @param[in] Wrapper Pointer to Wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyLaneControl ( IN LANE_CONTROL Control, IN UINT32 LaneBitMap, IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8023_STRUCT D0F0xE4_WRAP_8023; D0F0xE4_WRAP_8023.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), Pcie ); if (Control == EnableLanes) { D0F0xE4_WRAP_8023.Value |= LaneBitMap; } else if (Control == DisableLanes) { D0F0xE4_WRAP_8023.Value &= (~LaneBitMap); } D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1); PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), D0F0xE4_WRAP_8023.Value, TRUE, Pcie ); }
/** * Init SRBM reset * * @param[in] SrbmResetEnable SRBM reset enable flag. * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyInitSrbmReset ( IN BOOLEAN SrbmResetEnable, IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8063_STRUCT D0F0xE4_WRAP_8063; D0F0xE4_WRAP_8063.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS), Pcie ); if (SrbmResetEnable) { D0F0xE4_WRAP_8063.Field.ResetSrbm0En = 0x1; D0F0xE4_WRAP_8063.Field.ResetSrbm1En = 0x1; D0F0xE4_WRAP_8063.Field.ResetSrbmNbEn = 0x1; D0F0xE4_WRAP_8063.Field.ResetSrbmGfxEn = 0x1; D0F0xE4_WRAP_8063.Field.ResetSrbmDcEn = 0x1; } else { D0F0xE4_WRAP_8063.Field.ResetSrbm0En = 0x0; D0F0xE4_WRAP_8063.Field.ResetSrbm1En = 0x0; D0F0xE4_WRAP_8063.Field.ResetSrbmNbEn = 0x0; D0F0xE4_WRAP_8063.Field.ResetSrbmGfxEn = 0x0; D0F0xE4_WRAP_8063.Field.ResetSrbmDcEn = 0x0; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS), D0F0xE4_WRAP_8063.Value, FALSE, Pcie ); }
/** * Cleanup reconfig * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID STATIC PcieTopologyCleanUpReconfigCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101; UINT8 CoreId; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyCleanUpReconfigCZ Enter\n"); if (PcieLibIsPcieWrapper (Wrapper)) { for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { D0F0xE4_CORE_0101.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (CoreId, D0F0xE4_CORE_0101_ADDRESS), Pcie ); D0F0xE4_CORE_0101.Field.CONFIG_XFER_MODE = 0x1; PcieRegisterWrite ( Wrapper, CORE_SPACE (CoreId, D0F0xE4_CORE_0101_ADDRESS), D0F0xE4_CORE_0101.Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyCleanUpReconfigCZ Exit\n"); }
/** * Lanes enable/disable control * * @param[in] Control Lane control action * @param[in] LaneBitMap Core lanes bitmap * @param[in] Wrapper Pointer to Wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyLaneControlCZ ( IN LANE_CONTROL Control, IN UINT32 LaneBitMap, IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_CORE_0129_STRUCT D0F0xE4_CORE_0129; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyLaneControlCZ Enter\n"); D0F0xE4_CORE_0129.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0129_ADDRESS), Pcie ); if (Control == EnableLanes) { D0F0xE4_CORE_0129.Value |= LaneBitMap; } else if (Control == DisableLanes) { D0F0xE4_CORE_0129.Value &= (~LaneBitMap); } D0F0xE4_CORE_0129.Value &= ((1 << Wrapper->NumberOfLanes) - 1); PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0129_ADDRESS), D0F0xE4_CORE_0129.Value, TRUE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyLaneControlCZ Exit\n"); }
/** * Execute/clean up reconfiguration * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyExecuteReconfigV4 ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; PCIe_SILICON_CONFIG *Silicon; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n"); PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), Pcie ); D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); Silicon = PcieConfigGetParentSilicon (Wrapper); GnbLibPciIndirectRMW ( Silicon->Address.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_x1F630_ADDRESS, AccessWidth32, (UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK, Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET, GnbLibGetHeader (Pcie) ); GnbSmuServiceRequestV4 ( Silicon->Address, SMC_MSG_RECONFIGURE, 0, GnbLibGetHeader (Pcie) ); D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n"); } }
AGESA_STATUS STATIC PcieTopologySetCoreConfigCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, OUT BOOLEAN *ConfigChanged, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 CoreId; AGESA_STATUS Status; D0F0xE4_WRAP_0080_STRUCT D0F0xE4_WRAP_0080; Status = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Enter\n"); if (PcieLibIsPcieWrapper (Wrapper)) { for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { UINT64 ConfigurationSignature; UINT8 NewConfigurationValue; ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); if (Status == AGESA_SUCCESS) { D0F0xE4_WRAP_0080.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), Pcie ); IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s Original configuration - %s\n", PcieFmDebugGetWrapperNameString (Wrapper), CoreId, PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue), PcieFmDebugGetCoreConfigurationString (Wrapper, (UINT8) D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig) ); if (ConfigChanged != NULL) { if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) { *ConfigChanged = TRUE; } } D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), D0F0xE4_WRAP_0080.Value, FALSE, Pcie ); } else { IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", PcieFmDebugGetWrapperNameString (Wrapper), ((UINT32*)&ConfigurationSignature)[1], ((UINT32*)&ConfigurationSignature)[0] ); PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); } } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetCoreConfigCZ Exit\n"); return Status; }
/** * Execute/clean up reconfiguration * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyExecuteReconfigV5 ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; PCIe_SILICON_CONFIG *Silicon; DEV_OBJECT DevObject; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Enter\n"); D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), Pcie ); D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x0; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); Silicon = PcieConfigGetParentSilicon (Wrapper); DevObject.StdHeader = GnbLibGetHeader (Pcie); DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue; GnbSmuServiceRequestV7 ( &DevObject, SMC_MSG_RECONFIGURE, Wrapper->WrapId, 0 ); D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Exit\n"); } }
UINT32 PcieTimerGetTimeStamp ( IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_80F0_STRUCT D0F0xE4_WRAP_80F0; D0F0xE4_WRAP_80F0.Value = PcieRegisterRead ( (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_WRAPPER, &Pcie->Header), WRAP_SPACE (0, D0F0xE4_WRAP_80F0_ADDRESS), Pcie ); return D0F0xE4_WRAP_80F0.Value; }
VOID PciePifPllConfigureML ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureML Enter\n"); D0F0xE4_PIF_0012.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), Pcie ); D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0; if (Wrapper->Features.PowerOffUnusedPlls != 0) { D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; } else { D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0; D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0; } if (Wrapper->Features.PllOffInL1 != 0) { D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; } else { D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; } PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), D0F0xE4_PIF_0012.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + 1), D0F0xE4_PIF_0012.Value, TRUE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureML Exit\n"); }
/** * Init core registers. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID STATIC PcieEarlyCoreInitTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 CoreId; UINTN Index; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n"); for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { for (Index = 0; Index < CoreInitTableTN.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg), Pcie ); Value &= (~CoreInitTableTN.Table[Index].Mask); Value |= CoreInitTableTN.Table[Index].Data; PcieRegisterWrite ( Wrapper, CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg), Value, FALSE, Pcie ); } if (GnbBuildOptionsTN.CfgLinkBwNotificationEn == FALSE) { PcieRegisterRMW ( Wrapper, CORE_SPACE (CoreId, D0F0xE4_CORE_00C1_ADDRESS), D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK, 0 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n"); } }
VOID STATIC PcieTopologySelectMasterPllCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, OUT BOOLEAN *ConfigChanged, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_CORE_0118_STRUCT D0F0xE4_CORE_0118; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPllCZ Enter\n"); D0F0xE4_CORE_0118.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0118_ADDRESS), Pcie ); // // CZ PCIE master pll always select PHY0 (0 <= lane <= 7) // if (Wrapper->MasterPll == GNB_PCIE_MASTERPLL_A) { D0F0xE4_CORE_0118.Field.MASTER_PCIE_PLL_SELECT = 0x0; } else { D0F0xE4_CORE_0118.Field.MASTER_PCIE_PLL_SELECT = 0x1; } if (ConfigChanged != NULL) { *ConfigChanged = (D0F0xE4_CORE_0118.Field.MASTER_PCIE_PLL_SELECT == 0) ? FALSE : TRUE; } PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0118_ADDRESS), D0F0xE4_CORE_0118.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPllCZ Exit\n"); }
/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhy ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8040_STRUCT D0F0xE4_WRAP_8040; UINT32 LaneBitmap; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); D0F0xE4_WRAP_8040.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), Pcie ); if ((LaneBitmap & BIT0) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyA = 0x1; } if ((LaneBitmap & BIT4) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyB = 0x1; } if ((LaneBitmap & BIT8) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyC = 0x1; } if ((LaneBitmap & BIT12) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyD = 0x1; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), D0F0xE4_WRAP_8040.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); } }
/** * Prepare for reconfiguration * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyPrepareForReconfig ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; UINT8 CoreId; if (PcieLibIsPcieWrapper (Wrapper)) { for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { PcieRegisterWriteField ( Wrapper, CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), D0F0xE4_CORE_0011_DynClkLatency_OFFSET, D0F0xE4_CORE_0011_DynClkLatency_WIDTH, 0xf, FALSE, Pcie ); } D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), Pcie ); D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0; D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); } }
VOID PciePwrClockGating ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; UINT8 CoreId; IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n"); D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), Pcie ); D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), Pcie ); D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), Pcie ); D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), Pcie ); if (Wrapper->Features.ClkGating == 0x1) { D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1; D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1; D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1; D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f; D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f; D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f; D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7; D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1; D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1; D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1; D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1; D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0; D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1; D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f; D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1; D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1; } if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), D0F0xE4_WRAP_8014.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), D0F0xE4_WRAP_8015.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), D0F0xE4_WRAP_8012.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), D0F0xE4_WRAP_8011.Value, TRUE, Pcie ); for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { PcieRegisterWriteField ( Wrapper, CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), D0F0xE4_CORE_0011_DynClkLatency_OFFSET, D0F0xE4_CORE_0011_DynClkLatency_WIDTH, 0xf, TRUE, Pcie ); } if (Wrapper->Features.LclkGating == 0x1) { D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), Pcie ); D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), D0F0xE4_WRAP_8016.Value, TRUE, Pcie ); } IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n"); }
/** * Execute/clean up reconfiguration * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieTopologyExecuteReconfig ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n"); PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), Pcie ); D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), Pcie ); D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), D0F0xE4_WRAP_8060.Value, FALSE, Pcie ); do { D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), Pcie ); } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1); D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), D0F0xE4_WRAP_8062.Value, FALSE, Pcie ); PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n"); } }
VOID PcieTopologySelectMasterPll ( IN PCIe_WRAPPER_CONFIG *Wrapper, OUT BOOLEAN *ConfigChanged, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIe_ENGINE_CONFIG *EngineList; UINT16 MasterLane; UINT16 MasterHotplugLane; D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); MasterLane = 0xFFFF; MasterHotplugLane = 0xFFFF; EngineList = PcieConfigGetChildEngine (Wrapper); while (EngineList != NULL) { if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) { if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList); } else { MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); if (PcieConfigIsSbPcieEngine (EngineList)) { break; } } } EngineList = PcieLibGetNextDescriptor (EngineList); } if (MasterLane == 0xffff) { if (MasterHotplugLane != 0xffff) { MasterLane = MasterHotplugLane; } else { MasterLane = 0x0; } } D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), Pcie ); D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value; if ( MasterLane <= 3 ) { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; Wrapper->MasterPll = 0xA; } else if (MasterLane <= 7) { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; Wrapper->MasterPll = 0xB; } else if (MasterLane <= 11) { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; Wrapper->MasterPll = 0xC; } else { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1; Wrapper->MasterPll = 0xD; } if (ConfigChanged != NULL) { *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), D0F0xE4_WRAP_8013.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); }
/** * Set Dll Cap based on fuses * * * * @param[in] Wrapper Pointer to Wrapper configuration data area * @param[in] Pcie Pointer to PCIe configuration data area */ VOID PcieSetDllCapTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D18F3x1FC_STRUCT D18F3x1FC; D0F0xE4_PHY_500F_STRUCT D0F0xE4_PHY_500F; D0F0xE4_PHY_4010_STRUCT D0F0xE4_PHY_4010; D0F0xE4_PHY_4011_STRUCT D0F0xE4_PHY_4011; UINT32 Gen1Index; UINT32 Gen2Index; CPU_LOGICAL_ID LogicalId; GNB_HANDLE *GnbHandle; IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n"); D0F0xE4_PHY_500F.Value = 0; GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); ASSERT (GnbHandle != NULL); GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie)); //Read SWDllCapTableEn GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie)); IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value); if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & AMD_F15_TN_A0) != AMD_F15_TN_A0 )) { IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n"); // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0]) IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS)); D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value); // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0]) IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS)); D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value); // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0 // Else... // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl); if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) { IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp); Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1; } else { IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case..."); switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) { case 0: IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n"); Gen1Index = 0xd; break; case 1: IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n"); Gen1Index = 0xf; break; case 2: IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n"); Gen1Index = 0xa; break; default: IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n"); Gen1Index = 0xd; //Use typical for default case break; } } D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index; IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index); // Bits 3:0 = Gen1Index[3:0] // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0] if (D18F3x1FC.Field.SWDllCapTableEn != 0) { IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50); Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50; } else { Gen2Index = 0x03; // Hard coded default } D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index; IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index); PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); // Set DllProcessFreqCtlOverride on second write D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); if (Wrapper->WrapId == 1) { // For Wrapper 1, configure PHY0 and PHY1 D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); // Set DllProcessFreqCtlOverride on second write D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), D0F0xE4_PHY_500F.Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n"); }
VOID PcieTopologySelectMasterPll ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIe_ENGINE_CONFIG *EngineList; UINT16 MasterPhyLane; UINT16 MasterHotplugPhyLane; D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; EngineList = PcieWrapperGetEngineList (Wrapper); MasterPhyLane = 0xffff; MasterHotplugPhyLane = 0xffff; IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); while (EngineList != NULL) { if (PcieLibIsEngineAllocated (EngineList)) { if (EngineList->EngineData.EngineType == PciePortEngine) { MasterPhyLane = EngineList->EngineData.StartLane; if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { MasterHotplugPhyLane = MasterPhyLane; } } } EngineList = PcieLibGetNextDescriptor (EngineList); } if (MasterPhyLane == 0xffff) { MasterPhyLane = MasterHotplugPhyLane; if (MasterPhyLane == 0xffff) { MasterPhyLane = Wrapper->StartPhyLane; } } D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), Pcie ); MasterPhyLane = MasterPhyLane - Wrapper->StartPhyLane; if ( MasterPhyLane <= 3 ) { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; } else if (MasterPhyLane <= 7) { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; } else if (MasterPhyLane <= 11) { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; } else { D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), D0F0xE4_WRAP_8013.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); }
AGESA_STATUS STATIC PcieMidWrapperCharacterizationCallbackKV ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIe_WRAPPER_INFO *WrapperInfo; UINT8 Pif; D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; UINT8 ActualL1Latency; WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]); WrapperInfo->ActualL1Latency = EI_CYCLING_TIME + PLL_RAMP_UP_TIME + LS2_EXIT_TIME + RECOVER_TO_L0_TIME; if (WrapperInfo->MinAspmL1ExitLatency < WrapperInfo->ActualL1Latency) { WrapperInfo->ActualL1Latency -= EI_CYCLING_TIME; for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { PcieRegisterRMW ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), D0F0xE4_PIF_0010_EiDetCycleMode_MASK, (0 << D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET), TRUE, Pcie ); } } if (WrapperInfo->MinAspmL1ExitLatency < WrapperInfo->ActualL1Latency) { WrapperInfo->ActualL1Latency -= PLL_RAMP_UP_TIME; D0F0xE4_PIF_0012.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), Pcie ); D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0; D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0; for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), D0F0xE4_PIF_0012.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS + 1), D0F0xE4_PIF_0012.Value, TRUE, Pcie ); } WrapperInfo->AnyDevFailPllpdnb = TRUE; } if (WrapperInfo->MinAspmL1ExitLatency < WrapperInfo->ActualL1Latency) { WrapperInfo->DisableL1OnWrapper = TRUE; } ActualL1Latency = WrapperInfo->ActualL1Latency >> 1; WrapperInfo->L1ExitLatencyValue = 1; while (ActualL1Latency != 0) { ActualL1Latency = ActualL1Latency >> 1; WrapperInfo->L1ExitLatencyValue++; } return (AGESA_SUCCESS); }
/** * PHY lane parameter Init * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Buffer Pointer to buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PciePhyLaneInitInitCallbackCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; UINTN Index; IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackCZ Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, Wrapper); if (LaneBitmap == 0) { IDS_HDT_CONSOLE (GNB_TRACE, "No device allocated in this wrapper\n"); return AGESA_SUCCESS; } LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; if ((LaneBitmap & (1 << Lane)) != 0) { for (Index = 0; Index < PhyLaneInitEarlyTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyLaneInitEarlyTableCZ.Table[Index].Reg + (PhyLaneIndex * 0x100)), Pcie ); Value &= (~PhyLaneInitEarlyTableCZ.Table[Index].Mask); Value |= PhyLaneInitEarlyTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyLaneInitEarlyTableCZ.Table[Index].Reg + (PhyLaneIndex * 0x100)), Value, FALSE, Pcie ); } } } for (Lane = 0; Lane < Wrapper->NumberOfLanes; Lane += MAX_NUM_LANE_PER_PHY) { Phy = Lane / MAX_NUM_LANE_PER_PHY; for (Index = 0; Index < PhyWrapperInitEarlyTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyWrapperInitEarlyTableCZ.Table[Index].Reg), Pcie ); Value &= (~PhyWrapperInitEarlyTableCZ.Table[Index].Mask); Value |= PhyWrapperInitEarlyTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyWrapperInitEarlyTableCZ.Table[Index].Reg), Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackCZ Exit\n"); return AGESA_SUCCESS; }
/** * Execute/clean up reconfiguration * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID STATIC PcieTopologyExecuteReconfigCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101; PCIe_SILICON_CONFIG *Silicon; DEV_OBJECT DevObject; UINT32 SmuArg[6]; if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Enter\n"); D0F0xE4_CORE_0101.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS), Pcie ); D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x1; D0F0xE4_CORE_0101.Field.RESET_PERIOD = 0x2; PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS), D0F0xE4_CORE_0101.Value, FALSE, Pcie ); Silicon = PcieConfigGetParentSilicon (Wrapper); DevObject.StdHeader = GnbLibGetHeader (Pcie); DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue; LibAmdMemFill (SmuArg, 0x00, sizeof (SmuArg), GnbLibGetHeader (Pcie)); SmuArg [0] = Wrapper->WrapId; GnbSmuServiceRequestV8 ( &DevObject, SMC_MSG_RECONFIGURE_SB, SmuArg, 0 ); D0F0xE4_CORE_0101.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS), Pcie ); D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x0; PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS), D0F0xE4_CORE_0101.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Exit\n"); } }
VOID STATIC PcieMidPortInitCallbackKV ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { DxFxx68_STRUCT DxFxx68; D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; PCIe_SUBLINK_INFO *SublinkInfo; PCIe_WRAPPER_INFO *WrapperInfo; PCIe_WRAPPER_CONFIG *Wrapper; CPU_LOGICAL_ID LogicalId; UINT8 Count; UINT8 Nibble; PciePortProgramRegisterTable (PortInitMidTableKV.Table, PortInitMidTableKV.Length, Engine, TRUE, Pcie); if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { PcieEnableSlotPowerLimitV5 (Engine, Pcie); if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) { PcieInitPortForIommuV4 (Engine, Pcie); } // After GFX link is trained up and before ASPM is enabled, AGESA needs to check link width, // if it equals to x16, then apply the following change to GFX port: // Per port register 0xA1 - PCIE LC TRAINING CONTROL, bit16 - LC_EXTEND_WAIT_FOR_SKP = 1 GnbLibPciRead ( Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, AccessWidth32, &DxFxx68, GnbLibGetHeader (Pcie) ); if (DxFxx68.Field.NegotiatedLinkWidth == 16) { PciePortRegisterRMW ( Engine, DxFxxE4_xA1_ADDRESS, DxFxxE4_xA1_LcExtendWaitForSkp_MASK, (1 << DxFxxE4_xA1_LcExtendWaitForSkp_OFFSET), TRUE, Pcie ); } } Wrapper = PcieConfigGetParentWrapper (Engine); SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]); WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]); GetLogicalIdOfCurrentCore (&LogicalId, (AMD_CONFIG_PARAMS *)Pcie->StdHeader); // Check if this CPU is KV A0 // UBTS468566 if ((LogicalId.Revision & AMD_F15_KV_A0) != 0) { Count = SublinkInfo->GppPortCount; IDS_HDT_CONSOLE (GNB_TRACE, "x1x2 PortCount = %02x\n", Count); if (Count == 2) { // If number of GPP ports under the same sublink is 2, Delay L1 Exit (prolong minimum time spent in L1) PciePortRegisterRMW ( Engine, DxFxxE4_xA0_ADDRESS, DxFxxE4_xA0_LcDelayCount_MASK | DxFxxE4_xA0_LcDelayL1Exit_MASK, (0 << DxFxxE4_xA0_LcDelayCount_OFFSET) | (1 << DxFxxE4_xA0_LcDelayL1Exit_OFFSET), TRUE, Pcie ); } else if (Count > 2) { // If number of GPP ports > 2 if (SublinkInfo->MaxGenCapability > Gen1) { // If at least 1 GPP is Gen2 capable, Disable PLL Power down feature Wrapper = PcieConfigGetParentWrapper (Engine); Nibble = (UINT8) ((MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) % 8) / 4); // Only PSD and PPD can have x1/x2 links, so we assume that PIF number is always 0 D0F0xE4_PIF_0012.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble), Pcie ); D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0; D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0; PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble), D0F0xE4_PIF_0012.Value, TRUE, Pcie ); } else { // All ports are only Gen1 PciePortRegisterRMW ( Engine, DxFxxE4_xC0_ADDRESS, DxFxxE4_xC0_StrapMedyTSxCount_MASK, 0x2 << DxFxxE4_xC0_StrapMedyTSxCount_OFFSET, TRUE, Pcie ); } } } PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0802_ADDRESS + (0x100 * Engine->Type.Port.PortId)), D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_MASK, (WrapperInfo->L1ExitLatencyValue << D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_OFFSET), TRUE, Pcie ); if (WrapperInfo->DisableL1OnWrapper == TRUE) { Engine->Type.Port.PortData.LinkAspm &= ~(AspmL1); } PcieEnableAspm (Engine, Pcie); }
VOID STATIC PcieHwInitPowerGatingCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Pif; UINT32 Value; D0F0xE4_PIF_0004_STRUCT D0F0xE4_PIF_0004; D0F0xE4_PIF_0008_STRUCT D0F0xE4_PIF_0008; D0F0xE4_PIF_000A_STRUCT D0F0xE4_PIF_000A; D0F0xE4_CORE_012A_STRUCT D0F0xE4_CORE_012A; D0F0xE4_CORE_012C_STRUCT D0F0xE4_CORE_012C; D0F0xE4_CORE_012D_STRUCT D0F0xE4_CORE_012D; GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData; IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Enter\n"); GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie)); ASSERT (GnbBuildOptionData != NULL); Value = 0x0; if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) { Value = 0x1; } PcieRegisterWriteField ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_003D_ADDRESS), D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_OFFSET, D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_WIDTH, Value, TRUE, Pcie ); for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { D0F0xE4_PIF_0008.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS), Pcie ); D0F0xE4_PIF_000A.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS), Pcie ); D0F0xE4_PIF_0008.Field.TxpwrInOff = GnbBuildOptionData->CfgPcieTxpwrInOff; D0F0xE4_PIF_000A.Field.RxpwrInOff = GnbBuildOptionData->CfgPcieRxpwrInOff; D0F0xE4_PIF_000A.Field.RxEiDetInPs2Degrade = 0x0; D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x0; D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x0; if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) { D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x1; D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x1; } D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x0; D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x0; if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingOffPg) == PcieHwInitPwrGatingOffPg) { D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x1; D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x1; } PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS), D0F0xE4_PIF_0008.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS), D0F0xE4_PIF_000A.Value, TRUE, Pcie ); D0F0xE4_PIF_0004.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS), Pcie ); D0F0xE4_PIF_0004.Field.PifDegradePwrPllMode = 0x0; PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS), D0F0xE4_PIF_0004.Value, TRUE, Pcie ); } D0F0xE4_CORE_012A.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS), Pcie ); D0F0xE4_CORE_012C.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS), Pcie ); D0F0xE4_CORE_012D.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS), Pcie ); D0F0xE4_CORE_012A.Field.LMLaneDegrade0 = 1; D0F0xE4_CORE_012A.Field.LMLaneDegrade1 = 1; D0F0xE4_CORE_012A.Field.LMLaneDegrade2 = 1; D0F0xE4_CORE_012A.Field.LMLaneDegrade3 = 1; D0F0xE4_CORE_012C.Field.LMLaneUnused0 = 1; D0F0xE4_CORE_012C.Field.LMLaneUnused1 = 1; D0F0xE4_CORE_012C.Field.LMLaneUnused2 = 1; D0F0xE4_CORE_012D.Field.LMLaneUnused3 = 1; PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS), D0F0xE4_CORE_012A.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS), D0F0xE4_CORE_012C.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS), D0F0xE4_CORE_012D.Value, TRUE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Exit\n"); }