VOID PciePwrPowerDownUnusedLanes ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 UnusedLanes; IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); if (Wrapper->Features.PowerOffUnusedLanes != 0) { UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); PcieTopologyLaneControl ( DisableLanes, UnusedLanes, Wrapper, Pcie ); } if (Wrapper->Features.PowerOffUnusedPlls != 0) { UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, Wrapper); PciePifPllPowerDown ( UnusedLanes, Wrapper, Pcie ); } IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); }
VOID PciePwrPowerDownUnusedLanes ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 UnusedLanes; UINT32 AllLanes; IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); if (Wrapper->Features.PowerOffUnusedPlls != 0) { AllLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Wrapper); if (AllLanes != UnusedLanes) { //Some lanes end up beeing used. We should keep master PLL powered up UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, Wrapper); } PciePifPllPowerDown ( UnusedLanes, Wrapper, Pcie ); } if (Wrapper->Features.PowerOffUnusedLanes != 0) { UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); PcieTopologyLaneControl ( DisableLanes, UnusedLanes, Wrapper, Pcie ); } IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); }
/** * PHY Pll Personality Init Callback * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Buffer Pointer to buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS PciePhyLetPllPersonalityInitCallbackTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n"); PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie); PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); PciePollPifForCompeletion (Wrapper, Pcie); PcieTopologyLaneControl ( DisableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), Wrapper, Pcie ); PciePollPifForCompeletion (Wrapper, Pcie); PcieSetPhyPersonalityTN (Wrapper, Pcie); PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); PciePollPifForCompeletion (Wrapper, Pcie); PcieTopologyLaneControl ( EnableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), Wrapper, Pcie ); PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); PciePollPifForCompeletion (Wrapper, Pcie); PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n"); return AGESA_SUCCESS; }
/** * Per wrapper Pcie Init prior training. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Buffer Pointer buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PcieEarlyInitCallbackTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; BOOLEAN CoreConfigChanged; BOOLEAN PllConfigChanged; IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n"); CoreConfigChanged = FALSE; PllConfigChanged = FALSE; PcieTopologyPrepareForReconfig (Wrapper, Pcie); Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie); ASSERT (Status == AGESA_SUCCESS); PcieTopologyApplyLaneMux (Wrapper, Pcie); PciePifSetRxDetectPowerMode (Wrapper, Pcie); PciePifSetLs2ExitTime (Wrapper, Pcie); PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie); if (CoreConfigChanged || PllConfigChanged) { PcieTopologyExecuteReconfigV4 (Wrapper, Pcie); } PcieTopologyCleanUpReconfig (Wrapper, Pcie); PcieTopologySetLinkReversalV4 (Wrapper, Pcie); if (Wrapper->Features.PowerOffUnusedPlls != 0) { PciePifPllPowerDown ( PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper), Wrapper, Pcie ); PciePifPllInitForDdi (Wrapper, Pcie); PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie); } PcieTopologyLaneControl ( DisableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), Wrapper, Pcie ); PcieSetReciverTerminationTN (Wrapper, Pcie); PcieSetDdiOwnPhyV4 (Wrapper, Pcie); PciePollPifForCompeletion (Wrapper, Pcie); PciePhyAvertClockPickers (Wrapper, Pcie); PcieEarlyCoreInitTN (Wrapper, Pcie); PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); if (PcieConfigIsPcieWrapper (Wrapper)) { PcieSetDllCapTN (Wrapper, Pcie); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status); return Status; }
/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhyV4 ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmap; UINT8 Slice; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); for (Slice = 0; Slice < 4; Slice++) { if ((LaneBitmap & (1 << (Slice * 4))) != 0) { PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice), D0F0xE4_WRAP_8040_OwnSlice_MASK, 1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n"); } }
/** * Per wrapper Pcie Init prior training. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Buffer Pointer buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS PcieInitCallback ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; PcieTopologyPrepareForReconfig (Wrapper, Pcie); Status = PcieTopologySetCoreConfig (Wrapper, Pcie); ASSERT (Status == AGESA_SUCCESS); PcieTopologyApplyLaneMux (Wrapper, Pcie); PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie); PciePifSetLs2ExitTime (Wrapper, Pcie); PcieTopologySelectMasterPll (Wrapper, Pcie); PcieTopologyExecuteReconfig (Wrapper, Pcie); PcieTopologySetLinkReversal (Wrapper, Pcie); PciePifApplyGanging (Wrapper, Pcie); PcieFmPhyApplyGanging (Wrapper, Pcie); PciePifPllInitForDdi (Wrapper, Pcie); PcieTopologyLaneControl ( DisableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), Wrapper, Pcie ); PcieSetDdiOwnPhy (Wrapper, Pcie); PciePollPifForCompeletion (Wrapper, Pcie); PcieFmAvertClockPickers (Wrapper, Pcie); PcieCommonCoreInit (Wrapper, Pcie); PciePifDisableFifoReset (Wrapper, Pcie); return Status; }
/** * PHY set the correct termination value for the unused lanes * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetReciverTerminationTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetReciverTerminationTN Enter\n"); if ((Wrapper->WrapId == GFX_WRAP_ID) || (Wrapper->WrapId == GPP_WRAP_ID)) { LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { if ((LaneBitmap & (1 << Lane)) != 0) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; PcieRegisterRMW ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_C005_ADDRESS + PhyLaneIndex * 0x80), D0F0xE4_PHY_C005_TermMode_MASK, (0x2 << D0F0xE4_PHY_C005_TermMode_OFFSET), FALSE, Pcie ); } } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetReciverTerminationTN Exit\n"); }
/** * Set TX control for PCIe lanes * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieWrapSetTxS1CtrlForLaneMux ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025; UINT32 LaneBitmap; UINTN Index; D0F0xE4_WRAP_8025.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), Pcie ); Index = 0; LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); while (LaneBitmap != 0) { if ((LaneBitmap & 0xf) != 0) { D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8))); D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8)); } LaneBitmap >>= 4; ++Index; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), D0F0xE4_WRAP_8025.Value, FALSE, Pcie ); }
UINT32 PcieLanesToPowerDownPllInL1 ( IN UINT8 PllPowerUpLatency, IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 LaneGroupExitLatency [4]; UINT32 LaneBitmapForPllOffInL1; PCIe_ENGINE_CONFIG *EngineList; UINTN Index; IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n"); LaneBitmapForPllOffInL1 = 0; if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) { if (Wrapper->Features.PllOffInL1 != 0) { LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie)); EngineList = PcieConfigGetChildEngine (Wrapper); while (EngineList != NULL) { PCIe_ASPM_LATENCY_INFO LinkLatencyInfo; UINT32 ActiveLanesBitmap; UINT32 HotplugLanesBitmap; if (EngineList->EngineData.EngineType == PciePortEngine) { LinkLatencyInfo.MaxL1ExitLatency = 0; LinkLatencyInfo.MaxL0sExitLatency = 0; ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList); HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList); if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) { PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie)); } if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) { LinkLatencyInfo.MaxL1ExitLatency = 0xff; } IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap); for (Index = 0; Index < 4; Index++) { if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; } } } } EngineList = PcieLibGetNextDescriptor (EngineList); } LaneBitmapForPllOffInL1 = 0; for (Index = 0; Index < 4; Index++) { IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); } } } } IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1); IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n"); return LaneBitmapForPllOffInL1; }
/** * RX offset cancellation enablement * * * * @param[in] Wrapper Pointer to Wrapper configuration data area * @param[in] Pcie Pointer to PCIe configuration data area */ VOID PcieOffsetCancelCalibration ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmap; D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) { return; } if (LaneBitmap != 0) { D0F0xBC_x1F39C.Value = 0; D0F0xBC_x1F39C.Field.Tx = 1; D0F0xBC_x1F39C.Field.Rx = 1; D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane; D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane; GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); GnbSmuServiceRequestV4 ( PcieConfigGetParentSilicon (Wrapper)->Address, SMC_MSG_PHY_LN_OFF, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie) ); GnbSmuServiceRequestV4 ( PcieConfigGetParentSilicon (Wrapper)->Address, SMC_MSG_PHY_LN_ON, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie) ); } PcieTopologyLaneControl ( EnableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper), Wrapper, Pcie ); }
/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhy ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmap; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ALLOCATED, 0, Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); } }
VOID PciePowerDownPllInL1CZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmapForPllOffInL1; UINT32 ActiveLaneBitmap; UINT8 PllPowerUpLatency; IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1CZ Enter\n"); ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); if (ActiveLaneBitmap != 0) { PllPowerUpLatency = PciePifGetPllPowerUpLatencyCZ (Wrapper, Pcie); LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie); if ((LaneBitmapForPllOffInL1 != 0) && ((ActiveLaneBitmap & LaneBitmapForPllOffInL1) == ActiveLaneBitmap)) { LaneBitmapForPllOffInL1 &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); LaneBitmapForPllOffInL1 |= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, 0, Wrapper); PciePifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie); } } IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1CZ Exit\n"); }
/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhy ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8040_STRUCT D0F0xE4_WRAP_8040; UINT32 LaneBitmap; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); D0F0xE4_WRAP_8040.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), Pcie ); if ((LaneBitmap & BIT0) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyA = 0x1; } if ((LaneBitmap & BIT4) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyB = 0x1; } if ((LaneBitmap & BIT8) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyC = 0x1; } if ((LaneBitmap & BIT12) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyD = 0x1; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), D0F0xE4_WRAP_8040.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); } }
AGESA_STATUS PcieFP2x8CheckCallbackTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmap; AGESA_STATUS Status; IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n"); Status = AGESA_SUCCESS; if (Wrapper->WrapId == GFX_WRAP_ID) { LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap); if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) { IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n"); Status = AGESA_ERROR; PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); PutEventLog ( AGESA_ERROR, GNB_EVENT_INVALID_LANES_CONFIGURATION, (LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane), (LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane), 0, 0, GnbLibGetHeader (Pcie) ); ASSERT (FALSE); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n"); return Status; }
/** * PHY lane parameter Init * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Buffer Pointer to buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS PciePhyLaneInitInitCallbackTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { if ((LaneBitmap & (1 << Lane)) != 0) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; PcieRegisterRMW ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80), D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), FALSE, Pcie ); PcieRegisterRMW ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80), D0F0xE4_PHY_4002_LfcMax_MASK, (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET), FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n"); return AGESA_SUCCESS; }
/** * Per wrapper Pcie Init prior training. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Buffer Pointer buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PcieEarlyInitCallbackCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; BOOLEAN CoreConfigChanged; BOOLEAN PllConfigChanged; BOOLEAN AriSupportEnable; GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData; IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackCZ Enter\n"); CoreConfigChanged = FALSE; PllConfigChanged = FALSE; GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie)); ASSERT (GnbBuildOptionData != NULL); AriSupportEnable = GnbBuildOptionData->CfgAriSupport; if (AriSupportEnable == TRUE) { // Enable Alternative Routing-ID Interpretation GnbLibPciIndirectRMW ( MAKE_SBDFO (0,0,0,0, D0F0x60_ADDRESS), D0F0x64_x46_ADDRESS, AccessWidth32, (UINT32)~D0F0x64_x46_IocAriSupported_MASK, (1 << D0F0x64_x46_IocAriSupported_OFFSET), GnbLibGetHeader (Pcie) ); PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0000_ADDRESS), D0F0xE4_WRAP_0000_StrapBif2AriEn_MASK, (1 << D0F0xE4_WRAP_0000_StrapBif2AriEn_OFFSET), TRUE, Pcie ); } if (GnbBuildOptionData->CfgACSEnable == TRUE) { // Enable Access Control Services PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_000A_ADDRESS), 0xFFFFFFF8, (BIT0 | BIT1 | BIT2), TRUE, Pcie ); } IDS_OPTION_HOOK (IDS_BEFORE_RECONFIGURATION, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader); PcieTopologyPrepareForReconfigCZ (Wrapper, Pcie); //step 2 Status = PcieTopologySetCoreConfigCZ (Wrapper, &CoreConfigChanged, Pcie); //step 3 ASSERT (Status == AGESA_SUCCESS); PcieTopologyApplyLaneMuxCZ (Wrapper, Pcie); //step 4 // PciePifSetRxDetectPowerMode (Wrapper, Pcie); // PciePifSetLs2ExitTime (Wrapper, Pcie); // PciePifApplyGanging (Wrapper, Pcie); // PciePhyApplyGangingCZ (Wrapper, Pcie); PcieTopologySelectMasterPllCZ (Wrapper, &PllConfigChanged, Pcie); //step 5 if (CoreConfigChanged) { PcieTopologyExecuteReconfigCZ (Wrapper, Pcie); // step 6 } PcieEarlyWrapperTxPresetLoadingSequenceCZ (Wrapper, Pcie); PcieTopologyCleanUpReconfigCZ (Wrapper, Pcie); // step 7 PcieTopologySetLinkReversalV4 (Wrapper, Pcie); // step 8 // PciePifPllConfigureCZ (Wrapper, Pcie); PcieTopologyLaneControlCZ ( DisableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), Wrapper, Pcie ); //step 9 // PciePollPifForCompeletion (Wrapper, Pcie); // PciePhyAvertClockPickersCZ (Wrapper, Pcie); PcieEarlyCoreInitCZ (Wrapper, Pcie); PcieSetSsidCZ (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); PcieHwInitPowerGatingCZ (Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackCZ Exit [%x]\n", Status); return Status; }
/** * PHY lane parameter Init * * * * @param[in] Wrapper Pointer to wrapper config descriptor * @param[in] Buffer Pointer to buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PciePhyLaneInitInitCallbackCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Phy; UINT8 PhyLaneIndex; UINT8 Lane; UINT32 LaneBitmap; UINTN Index; IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackCZ Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, Wrapper); if (LaneBitmap == 0) { IDS_HDT_CONSOLE (GNB_TRACE, "No device allocated in this wrapper\n"); return AGESA_SUCCESS; } LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { Phy = Lane / MAX_NUM_LANE_PER_PHY; PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; if ((LaneBitmap & (1 << Lane)) != 0) { for (Index = 0; Index < PhyLaneInitEarlyTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyLaneInitEarlyTableCZ.Table[Index].Reg + (PhyLaneIndex * 0x100)), Pcie ); Value &= (~PhyLaneInitEarlyTableCZ.Table[Index].Mask); Value |= PhyLaneInitEarlyTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyLaneInitEarlyTableCZ.Table[Index].Reg + (PhyLaneIndex * 0x100)), Value, FALSE, Pcie ); } } } for (Lane = 0; Lane < Wrapper->NumberOfLanes; Lane += MAX_NUM_LANE_PER_PHY) { Phy = Lane / MAX_NUM_LANE_PER_PHY; for (Index = 0; Index < PhyWrapperInitEarlyTableCZ.Length; Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyWrapperInitEarlyTableCZ.Table[Index].Reg), Pcie ); Value &= (~PhyWrapperInitEarlyTableCZ.Table[Index].Mask); Value |= PhyWrapperInitEarlyTableCZ.Table[Index].Data; PcieRegisterWrite ( Wrapper, PHY_SPACE (Wrapper->WrapId, Phy, PhyWrapperInitEarlyTableCZ.Table[Index].Reg), Value, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackCZ Exit\n"); return AGESA_SUCCESS; }