int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) { u32 pixel_format; u8 sw; /*Route I2C4 to DIU system as HSYNC/VSYNC*/ sw = QIXIS_READ(brdcfg[5]); QIXIS_WRITE(brdcfg[5], ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); /*Configure Display ouput port as HDMI*/ sw = QIXIS_READ(brdcfg[15]); QIXIS_WRITE(brdcfg[15], ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); return fsl_diu_init(xres, yres, pixel_format, 0); }
void qixis_dump_switch(void) { int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); nr_of_cfgsw = QIXIS_READ(cms[1]); puts("DIP switch settings dump:\n"); for (i = 1; i <= nr_of_cfgsw; i++) { QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } }
static void set_brdcfg9_for_gtx_clk(void) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); brdcfg9 |= (1 << 5); QIXIS_WRITE(brdcfg[9], brdcfg9); }
int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; #ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; #endif u32 val; init_final_memctl_regs(); val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); env_hwconfig = getenv("hwconfig"); if (hwconfig_f("dspi", env_hwconfig) && DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) config_board_mux(MUX_TYPE_DSPI); else config_board_mux(MUX_TYPE_SDHC); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); #ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif return 0; }
int board_early_init_f(void) { #ifdef CONFIG_HAS_FSL_XHCI_USB struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif #ifdef CONFIG_LPUART u8 uart; #endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); #endif fsl_lsch2_early_init_f(); #ifdef CONFIG_HAS_FSL_XHCI_USB out_be32(&scfg->rcwpmuxcr0, 0x3333); out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif #ifdef CONFIG_LPUART /* We use lpuart0 as system console */ uart = QIXIS_READ(brdcfg[14]); uart &= ~CFG_UART_MUX_MASK; uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; QIXIS_WRITE(brdcfg[14], uart); #endif return 0; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); set_liodns(); #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; }
static void ls1021a_mux_mdio(int addr) { u8 brdcfg4; brdcfg4 = QIXIS_READ(brdcfg[4]); brdcfg4 &= EMI1_MASK; switch (addr) { case EMI1_RGMII0: brdcfg4 |= 0; break; case EMI1_RGMII1: brdcfg4 |= 0x20; break; case EMI1_RGMII2: brdcfg4 |= 0x40; break; case EMI1_SGMII1: brdcfg4 |= 0x60; break; case EMI1_SGMII2: brdcfg4 |= 0x80; break; default: brdcfg4 |= 0xa0; break; } QIXIS_WRITE(brdcfg[4], brdcfg4); }
int config_board_mux(int ctrl_type) { u8 reg12, reg14; reg12 = QIXIS_READ(brdcfg[12]); reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { case MUX_TYPE_CAN: config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); break; case MUX_TYPE_IIC2: reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); break; case MUX_TYPE_RGMII: reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); break; case MUX_TYPE_SAI: config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); break; case MUX_TYPE_SDHC: reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); break; case MUX_TYPE_SD_PCI4: reg12 = 0x38; break; case MUX_TYPE_SD_PC_SA_SG_SG: reg12 = 0x01; break; case MUX_TYPE_SD_PC_SA_PC_SG: reg12 = 0x01; break; case MUX_TYPE_SD_PC_SG_SG: reg12 = 0x21; break; default: printf("Wrong mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[12], reg12); QIXIS_WRITE(brdcfg[14], reg14); return 0; }
/* Set the boot bank to the alternate bank */ void set_altbank(void) { u8 reg; reg = QIXIS_READ(brdcfg[0]); reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK; QIXIS_WRITE(brdcfg[0], reg); }
int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; if (argc <= 1) { clear_altbank(); qixis_reset(); } else if (strcmp(argv[1], "altbank") == 0) { set_altbank(); qixis_bank_reset(); } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", "1min", "2min", "4min", "8min"}; u8 rcfg = QIXIS_READ(rcfg_ctl); if (argv[2] == NULL) { printf("qixis watchdog <watchdog_period>\n"); return 0; } for (i = 0; i < ARRAY_SIZE(period); i++) { if (strcmp(argv[2], period[i]) == 0) { /* disable watchdog */ QIXIS_WRITE(rcfg_ctl, rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); QIXIS_WRITE(watch, ((i<<2) - 1)); QIXIS_WRITE(rcfg_ctl, rcfg); return 0; } } } #ifdef DEBUG else if (strcmp(argv[1], "dump") == 0) { qixis_dump_regs(); return 0; } #endif else { printf("Invalid option: %s\n", argv[1]); return 1; } return 0; }
static void set_brdcfg9_for_gtx_clk(void) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); /* Initializing EPHY2 clock to RGMII mode */ brdcfg9 &= ~(BRDCFG9_EPHY2_MASK); brdcfg9 |= (BRDCFG9_EPHY2_VAL); QIXIS_WRITE(brdcfg[9], brdcfg9); }
static void ls2080a_qds_enable_SFP_TX(u8 muxval) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); brdcfg9 &= ~BRDCFG9_SFPTX_MASK; brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT); QIXIS_WRITE(brdcfg[9], brdcfg9); }
static void t1040_qds_mux_mdio(u8 muxval) { u8 brdcfg4; if (muxval <= 7) { brdcfg4 = QIXIS_READ(brdcfg[4]); brdcfg4 &= ~BRDCFG4_EMISEL_MASK; brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); QIXIS_WRITE(brdcfg[4], brdcfg4); } }
int board_init(void) { init_final_memctl_regs(); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); return 0; }
int board_early_init_f(void) { #ifdef CONFIG_LPUART u8 uart; #endif fsl_lsch2_early_init_f(); #ifdef CONFIG_LPUART /* We use lpuart0 as system console */ uart = QIXIS_READ(brdcfg[14]); uart &= ~CFG_UART_MUX_MASK; uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; QIXIS_WRITE(brdcfg[14], uart); #endif return 0; }
int config_board_mux(int ctrl_type) { u8 reg14; reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { case MUX_TYPE_GPIO: reg14 = (reg14 & (~0x6)) | 0x2; break; default: puts("Unsupported mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[14], reg14); return 0; }
int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. */ /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); if (flash_esel == -1) { /* very unlikely unless something is messed up */ puts("Error: Could not find TLB for FLASH BASE\n"); flash_esel = 2; /* give our best effort to continue */ } else { /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. */ if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; }
int config_board_mux(int ctrl_type) { u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); switch (ctrl_type) { case MUX_TYPE_SDHC: reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); break; case MUX_TYPE_DSPI: reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); break; default: printf("Wrong mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[5], reg5); return 0; }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 srds_s1, srds_s2; u8 brdcfg12; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; srds_s2 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); switch (srds_s1) { case 0x3333: /* SGMII on slot 1, MAC 9 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); case 0x1333: case 0x2333: /* SGMII on slot 1, MAC 10 */ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); case 0x1133: case 0x2233: /* SGMII on slot 1, MAC 5/6 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x1040: case 0x2040: /* QSGMII on lane B, MAC 6/5/10/1 */ fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PORT1_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PORT2_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC10, QSGMII_CARD_PORT3_PHY_ADDR_S2); fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PORT4_PHY_ADDR_S2); break; case 0x3363: /* SGMII on slot 1, MAC 9/10 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); case 0x1163: case 0x2263: case 0x2223: /* SGMII on slot 1, MAC 6 */ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; default: printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", srds_s1); break; } if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) /* SGMII on slot 4, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { if (i == FM1_DTSEC5) { /* route lane 2 to slot1 so to have * one sgmii riser card supports * MAC5 and MAC6. */ brdcfg12 = QIXIS_READ(brdcfg[12]); QIXIS_WRITE(brdcfg[12], brdcfg12 | 0x80); } lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); } else { /* clear the bit 7 to route lane B on slot2. */ brdcfg12 = QIXIS_READ(brdcfg[12]); QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); lane_to_slot[lane] = 2; } if (i == FM1_DTSEC2) lane = 5; if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 1: mdio_mux[i] = EMI1_SLOT1; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; default: break; } break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_TXID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4) mdio_mux[i] = EMI1_RGMII2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int brd_mux_lane_to_slot(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_prtcl_s1; srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; #if defined(CONFIG_T2080QDS) u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; #endif switch (srds_prtcl_s1) { case 0: /* SerDes1 is not enabled */ break; #if defined(CONFIG_T2080QDS) case 0x1b: case 0x1c: case 0xa2: /* SD1(A:D) => SLOT3 SGMII * SD1(G:H) => SLOT1 SGMII */ QIXIS_WRITE(brdcfg[12], 0x1a); break; case 0x94: case 0x95: /* SD1(A:B) => SLOT3 [email protected] * SD1(C:D) => SFP Module, [email protected] * SD1(E:H) => SLOT1 [email protected] */ case 0x96: /* SD1(A:B) => SLOT3 [email protected] * SD1(C) => SFP Module, [email protected] * SD1(D) => SFP Module, [email protected] * SD1(E:H) => SLOT1 PCIe4 x4 */ QIXIS_WRITE(brdcfg[12], 0x3a); break; case 0x50: case 0x51: /* SD1(A:D) => SLOT3 XAUI * SD1(E) => SLOT1 PCIe4 * SD1(F:H) => SLOT2 SGMII */ QIXIS_WRITE(brdcfg[12], 0x15); break; case 0x66: case 0x67: /* SD1(A:D) => XFI cage * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xfe); break; case 0x6a: case 0x6b: /* SD1(A:D) => XFI cage * SD1(E) => SLOT1 PCIe4 * SD1(F:H) => SLOT2 SGMII */ QIXIS_WRITE(brdcfg[12], 0xf1); break; case 0x6c: case 0x6d: /* SD1(A:B) => XFI cage * SD1(C:D) => SLOT3 SGMII * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xda); break; case 0x6e: /* SD1(A:B) => SFP Module, XFI * SD1(C:D) => SLOT3 SGMII * SD1(E:F) => SLOT1 PCIe4 x2 * SD1(G:H) => SLOT2 SGMII */ QIXIS_WRITE(brdcfg[12], 0xd9); break; case 0xda: /* SD1(A:H) => SLOT3 PCIe3 x8 */ QIXIS_WRITE(brdcfg[12], 0x0); break; case 0xc8: /* SD1(A) => SLOT3 PCIe3 x1 * SD1(B) => SFP Module, [email protected] * SD1(C:D) => SFP Module, [email protected] * SD1(E:F) => SLOT1 PCIe4 x2 * SD1(G:H) => SLOT2 SGMII */ QIXIS_WRITE(brdcfg[12], 0x79); break; case 0xab: /* SD1(A:D) => SLOT3 PCIe3 x4 * SD1(E:H) => SLOT1 PCIe4 x4 */ QIXIS_WRITE(brdcfg[12], 0x1a); break; #elif defined(CONFIG_T2081QDS) case 0x50: case 0x51: /* SD1(A:D) => SLOT2 XAUI * SD1(E) => SLOT1 PCIe4 x1 * SD1(F:H) => SLOT3 SGMII */ QIXIS_WRITE(brdcfg[12], 0x98); QIXIS_WRITE(brdcfg[13], 0x70); break; case 0x6a: case 0x6b: /* SD1(A:D) => XFI SFP Module * SD1(E) => SLOT1 PCIe4 x1 * SD1(F:H) => SLOT3 SGMII */ QIXIS_WRITE(brdcfg[12], 0x80); QIXIS_WRITE(brdcfg[13], 0x70); break; case 0x6c: case 0x6d: /* SD1(A:B) => XFI SFP Module * SD1(C:D) => SLOT2 SGMII * SD1(E:H) => SLOT1 PCIe4 x4 */ QIXIS_WRITE(brdcfg[12], 0xe8); QIXIS_WRITE(brdcfg[13], 0x0); break; case 0xaa: case 0xab: /* SD1(A:D) => SLOT2 PCIe3 x4 * SD1(F:H) => SLOT1 SGMI4 x4 */ QIXIS_WRITE(brdcfg[12], 0xf8); QIXIS_WRITE(brdcfg[13], 0x0); break; case 0xca: case 0xcb: /* SD1(A) => SLOT2 PCIe3 x1 * SD1(B) => SLOT7 SGMII * SD1(C) => SLOT6 SGMII * SD1(D) => SLOT5 SGMII * SD1(E) => SLOT1 PCIe4 x1 * SD1(F:H) => SLOT3 SGMII */ QIXIS_WRITE(brdcfg[12], 0x80); QIXIS_WRITE(brdcfg[13], 0x70); break; case 0xde: case 0xdf: /* SD1(A:D) => SLOT2 PCIe3 x4 * SD1(E) => SLOT1 PCIe4 x1 * SD1(F) => SLOT4 PCIe1 x1 * SD1(G) => SLOT3 PCIe2 x1 * SD1(H) => SLOT7 SGMII */ QIXIS_WRITE(brdcfg[12], 0x98); QIXIS_WRITE(brdcfg[13], 0x25); break; case 0xf2: /* SD1(A) => SLOT2 PCIe3 x1 * SD1(B:D) => SLOT7 SGMII * SD1(E) => SLOT1 PCIe4 x1 * SD1(F) => SLOT4 PCIe1 x1 * SD1(G) => SLOT3 PCIe2 x1 * SD1(H) => SLOT7 SGMII */ QIXIS_WRITE(brdcfg[12], 0x81); QIXIS_WRITE(brdcfg[13], 0xa5); break; #endif default: printf("WARNING: unsupported for SerDes1 Protocol %d\n", srds_prtcl_s1); return -1; } #ifdef CONFIG_T2080QDS switch (srds_prtcl_s2) { case 0: /* SerDes2 is not enabled */ break; case 0x01: case 0x02: /* SD2(A:H) => SLOT4 PCIe1 */ QIXIS_WRITE(brdcfg[13], 0x10); break; case 0x15: case 0x16: /* * SD2(A:D) => SLOT4 PCIe1 * SD2(E:F) => SLOT5 PCIe2 * SD2(G:H) => SATA1,SATA2 */ QIXIS_WRITE(brdcfg[13], 0xb0); break; case 0x18: /* * SD2(A:D) => SLOT4 PCIe1 * SD2(E:F) => SLOT5 Aurora * SD2(G:H) => SATA1,SATA2 */ QIXIS_WRITE(brdcfg[13], 0x78); break; case 0x1f: /* * SD2(A:D) => SLOT4 PCIe1 * SD2(E:H) => SLOT5 PCIe2 */ QIXIS_WRITE(brdcfg[13], 0xa0); break; case 0x29: case 0x2d: case 0x2e: /* * SD2(A:D) => SLOT4 SRIO2 * SD2(E:H) => SLOT5 SRIO1 */ QIXIS_WRITE(brdcfg[13], 0xa0); break; case 0x36: /* * SD2(A:D) => SLOT4 SRIO2 * SD2(E:F) => Aurora * SD2(G:H) => SATA1,SATA2 */ QIXIS_WRITE(brdcfg[13], 0x78); break; default: printf("WARNING: unsupported for SerDes2 Protocol %d\n", srds_prtcl_s2); return -1; } #endif return 0; }
void qixis_reset(void) { QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); }
void qixis_bank_reset(void) { QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); }
/* * Initialize the lane_to_slot[] array. * * On the T1040QDS board the mapping is controlled by ?? register. */ static void initialize_lane_to_slot(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL) >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; QIXIS_WRITE(cms[0], 0x07); switch (serdes1_prtcl) { case 0x60: case 0x66: case 0x67: case 0x69: lane_to_slot[1] = 7; lane_to_slot[2] = 6; lane_to_slot[3] = 5; break; case 0x86: lane_to_slot[1] = 7; lane_to_slot[2] = 7; lane_to_slot[3] = 7; break; case 0x87: lane_to_slot[1] = 7; lane_to_slot[2] = 7; lane_to_slot[3] = 7; lane_to_slot[7] = 7; break; case 0x89: lane_to_slot[1] = 7; lane_to_slot[2] = 7; lane_to_slot[3] = 7; lane_to_slot[6] = 7; lane_to_slot[7] = 7; break; case 0x8d: lane_to_slot[1] = 7; lane_to_slot[2] = 7; lane_to_slot[3] = 7; lane_to_slot[5] = 3; lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; case 0x8F: case 0x85: lane_to_slot[1] = 7; lane_to_slot[2] = 6; lane_to_slot[3] = 5; lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; case 0xA5: lane_to_slot[1] = 7; lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; case 0xA7: lane_to_slot[1] = 7; lane_to_slot[2] = 6; lane_to_slot[3] = 5; lane_to_slot[7] = 7; break; case 0xAA: lane_to_slot[1] = 7; lane_to_slot[6] = 7; lane_to_slot[7] = 7; break; case 0x40: lane_to_slot[2] = 7; lane_to_slot[3] = 7; break; default: printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", serdes1_prtcl); break; } }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; struct memac_mdio_info tg_memac_mdio_info; unsigned int i; unsigned int serdes1_prtcl, serdes2_prtcl; int qsgmii; struct mii_dev *bus; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; if (!serdes1_prtcl) { printf("SERDES1 is not enabled\n"); return 0; } serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); serdes2_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; if (!serdes2_prtcl) { printf("SERDES2 is not enabled\n"); return 0; } serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); printf("Initializing Fman\n"); initialize_lane_to_slot(); memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); tg_memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_memac_mdio_init(bis, &tg_memac_mdio_info); /* * Program the two on board DTSEC PHY addresses assuming that they are * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and * 6 to on board SGMII phys */ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); switch (serdes1_prtcl) { case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n", CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n", CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); /* Fixing Serdes clock by programming FPGA register */ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #endif default: printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; } switch (serdes2_prtcl) { case 0x17: case 0x18: debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; case 0x48: case 0x49: debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); break; case 0xb1: case 0xb2: case 0x8c: case 0x8d: debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); /* * XFI does not need a PHY to work, but to make U-Boot * happy, assign a fake PHY address for a XFI port. */ fm_info_set_phy_address(FM1_10GEC1, 0); fm_info_set_phy_address(FM1_10GEC2, 1); break; case 0x98: /* XAUI in Slot1 and Slot2 */ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n", CONFIG_SYS_FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; case 0x9E: /* XAUI in Slot2 */ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; default: printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } /*set PHY address for QSGMII Riser Card on slot2*/ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); if (qsgmii) { switch (serdes2_prtcl) { case 0xb2: case 0x8d: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); break; default: break; } } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { int idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: fm_info_set_mdio(i, miiphy_get_dev_by_name (DEFAULT_FM_TGEC_MDIO_NAME)); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: TGEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int pfe_eth_board_init(struct udevice *dev) { static int init_done; struct mii_dev *bus; static const char *mdio_name; struct pfe_mdio_info mac_mdio_info; struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; u8 data8; struct pfe_eth_dev *priv = dev_get_priv(dev); int srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; ls1012aqds_mux_mdio(EMI1_SLOT1); if (!init_done) { mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; bus = pfe_mdio_init(&mac_mdio_info); if (!bus) { printf("Failed to register mdio\n"); return -1; } init_done = 1; } if (priv->gemac_port) { mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; bus = pfe_mdio_init(&mac_mdio_info); if (!bus) { printf("Failed to register mdio\n"); return -1; } } switch (srds_s1) { case 0x3508: printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); #ifdef CONFIG_PFE_RGMII_RESET_WA /* * Work around for FPGA registers initialization * This is needed for RGMII to work. */ printf("Reset RGMII WA....\n"); data8 = QIXIS_READ(rst_frc[0]); data8 |= 0x2; QIXIS_WRITE(rst_frc[0], data8); data8 = QIXIS_READ(rst_frc[0]); data8 = QIXIS_READ(res8[6]); data8 |= 0xff; QIXIS_WRITE(res8[6], data8); data8 = QIXIS_READ(res8[6]); #endif if (priv->gemac_port) { mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) < 0) { printf("Failed to register mdio for %s\n", mdio_name); } /* MAC2 */ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); bus = miiphy_get_dev_by_name(mdio_name); pfe_set_mdio(priv->gemac_port, bus); pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII); } else { mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) < 0) { printf("Failed to register mdio for %s\n", mdio_name); } /* MAC1 */ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); bus = miiphy_get_dev_by_name(mdio_name); pfe_set_mdio(priv->gemac_port, bus); pfe_set_phy_address_mode(priv->gemac_port, CONFIG_PFE_EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); } break; case 0x2205: printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); /* * Work around for FPGA registers initialization * This is needed for RGMII to work. */ printf("Reset SLOT1 SLOT2....\n"); data8 = QIXIS_READ(rst_frc[2]); data8 |= 0xc0; QIXIS_WRITE(rst_frc[2], data8); mdelay(100); data8 = QIXIS_READ(rst_frc[2]); data8 &= 0x3f; QIXIS_WRITE(rst_frc[2], data8); if (priv->gemac_port) { mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2) < 0) { printf("Failed to register mdio for %s\n", mdio_name); } /* MAC2 */ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); bus = miiphy_get_dev_by_name(mdio_name); pfe_set_mdio(1, bus); pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, PHY_INTERFACE_MODE_SGMII_2500); data8 = QIXIS_READ(brdcfg[12]); data8 |= 0x20; QIXIS_WRITE(brdcfg[12], data8); } else { mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) < 0) { printf("Failed to register mdio for %s\n", mdio_name); } /* MAC1 */ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); bus = miiphy_get_dev_by_name(mdio_name); pfe_set_mdio(0, bus); pfe_set_phy_address_mode(0, CONFIG_PFE_SGMII_2500_PHY1_ADDR, PHY_INTERFACE_MODE_SGMII_2500); } break; default: printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1); break; } return 0; }