static void qlcnic_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { struct qlcnic_adapter *adapter = netdev_priv(netdev); int port = adapter->ahw->physical_port; int err = 0; __u32 val; if (qlcnic_83xx_check(adapter)) { qlcnic_83xx_get_pauseparam(adapter, pause); return; } if (adapter->ahw->port_type == QLCNIC_GBE) { if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS)) return; /* get flow control settings */ val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), &err); if (err == -EIO) return; pause->rx_pause = qlcnic_gb_get_rx_flowctl(val); val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, &err); if (err == -EIO) return; switch (port) { case 0: pause->tx_pause = !(qlcnic_gb_get_gb0_mask(val)); break; case 1: pause->tx_pause = !(qlcnic_gb_get_gb1_mask(val)); break; case 2: pause->tx_pause = !(qlcnic_gb_get_gb2_mask(val)); break; case 3: default: pause->tx_pause = !(qlcnic_gb_get_gb3_mask(val)); break; } } else if (adapter->ahw->port_type == QLCNIC_XGBE) { if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS)) return; pause->rx_pause = 1; val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, &err); if (err == -EIO) return; if (port == 0) pause->tx_pause = !(qlcnic_xg_get_xg0_mask(val)); else pause->tx_pause = !(qlcnic_xg_get_xg1_mask(val)); } else { dev_err(&netdev->dev, "Unknown board type: %x\n", adapter->ahw->port_type); } }
static int qlcnic_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { struct qlcnic_adapter *adapter = netdev_priv(netdev); int port = adapter->ahw->physical_port; __u32 val; if (qlcnic_83xx_check(adapter)) return qlcnic_83xx_set_pauseparam(adapter, pause); /* read mode */ if (adapter->ahw->port_type == QLCNIC_GBE) { if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS)) return -EIO; /* set flow control */ val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port)); if (pause->rx_pause) qlcnic_gb_rx_flowctl(val); else qlcnic_gb_unset_rx_flowctl(val); QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), val); QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), val); /* set autoneg */ val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL); switch (port) { case 0: if (pause->tx_pause) qlcnic_gb_unset_gb0_mask(val); else qlcnic_gb_set_gb0_mask(val); break; case 1: if (pause->tx_pause) qlcnic_gb_unset_gb1_mask(val); else qlcnic_gb_set_gb1_mask(val); break; case 2: if (pause->tx_pause) qlcnic_gb_unset_gb2_mask(val); else qlcnic_gb_set_gb2_mask(val); break; case 3: default: if (pause->tx_pause) qlcnic_gb_unset_gb3_mask(val); else qlcnic_gb_set_gb3_mask(val); break; } QLCWR32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, val); } else if (adapter->ahw->port_type == QLCNIC_XGBE) { if (!pause->rx_pause || pause->autoneg) return -EOPNOTSUPP; if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS)) return -EIO; val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL); if (port == 0) { if (pause->tx_pause) qlcnic_xg_unset_xg0_mask(val); else qlcnic_xg_set_xg0_mask(val); } else { if (pause->tx_pause) qlcnic_xg_unset_xg1_mask(val); else qlcnic_xg_set_xg1_mask(val); } QLCWR32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, val); } else { dev_err(&netdev->dev, "Unknown board type: %x\n", adapter->ahw->port_type); } return 0; }