int main(void) { qm_rtc_config_t rtc_cfg; unsigned int count = 0; /* loop_max : Maximum number of iterations. * A value of 50 will run the application for roughly 30s. */ const unsigned int loop_max = 50; gpio_init(); pin_mux_setup(); gpio_set_out(BOARD_LED_PIN, 0); /* Configure the onboard LED pin. */ /* Clear Screen. */ QM_PUTS("Starting: Power Profiler"); QM_PUTS("Low power mode example."); QM_PRINTF("Increment = %d\n", QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1)); clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK); /* Initialise RTC configuration: Run, but don't interrupt. */ rtc_cfg.init_val = 0; rtc_cfg.alarm_en = 0; rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1); rtc_cfg.callback = rtc_example_callback; rtc_cfg.prescaler = CLK_RTC_DIV_1; qm_rtc_set_config(QM_RTC_0, &rtc_cfg); QM_IR_UNMASK_INT(QM_IRQ_RTC_0_INT); QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr); #if (!QM_SENSOR) test_clock_rates(); #endif /* Enable the RTC Interrupt. */ rtc_cfg.alarm_en = 1; qm_rtc_set_config(QM_RTC_0, &rtc_cfg); count = 0; while (++count < loop_max) { QM_PRINTF("\nC:%d R:%d => ", count, rtc_tick); slow_mode_test(); halt_test(); core_sleep_test(); /* TODO : Enable soc_sleep test for c1000. */ soc_sleep_test(); /* TODO : Enable soc_deep_sleep test for d2000 and c1000. */ soc_deep_sleep_test(); } SOC_WATCH_TRIGGER_FLUSH(); QM_PUTS("Finished: Power Profiler"); return 0; }
int main(void) { qm_rtc_config_t rtc_cfg; unsigned int count = 0; /* Maximum number of 3-second iterations. */ const unsigned int loop_max = 5; gpio_init(); gpio_set_out(BOARD_LED_PIN, 0); /* Configure the onboard LED pin. */ /* Clear Screen. */ QM_PUTS("Starting: Power Profiler"); QM_PUTS("Low power mode example."); QM_PRINTF("Increment = %d\n", QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1)); clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK); /* Initialise RTC configuration: Run, but don't interrupt. */ rtc_cfg.init_val = 0; rtc_cfg.alarm_en = 0; rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1); rtc_cfg.callback = rtc_example_callback; rtc_cfg.prescaler = CLK_RTC_DIV_1; qm_rtc_set_config(QM_RTC_0, &rtc_cfg); qm_irq_request(QM_IRQ_RTC_0_INT, qm_rtc_0_isr); test_clock_rates(); /* Enable the RTC Interrupt. */ rtc_cfg.alarm_en = 1; qm_rtc_set_config(QM_RTC_0, &rtc_cfg); count = 0; while (++count < loop_max) { QM_PRINTF("\nC:%d R:%d => ", count, rtc_tick); slow_mode_test(); halt_test(); sleep_test(); #if DEEP_SLEEP deep_sleep_test(); #endif } QM_PUTS("Finished: Power Profiler"); return 0; }
static void rtc_example_callback() { /* Log the interrupt event. */ SOC_WATCH_LOG_EVENT(SOCW_EVENT_INTERRUPT, QM_IRQ_RTC_0_INT_VECTOR); /* Invert On-board LED. */ led_flip(BOARD_LED_PIN); ++rtc_tick; /* Reschedule next tick. */ qm_rtc_set_alarm(QM_RTC_0, (QM_RTC[QM_RTC_0]->rtc_ccvr + (QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1) / 2))); }
int main(void) { qm_rtc_config_t rtc_cfg; uint32_t aonc_start; uint32_t rtc_trigger; /* Initialise RTC configuration. */ rtc_cfg.init_val = 0; /* Set initial value to 0. */ rtc_cfg.alarm_en = 1; /* Enable alarm. */ rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1); /* 1s alarm. */ rtc_cfg.callback = NULL; rtc_cfg.callback_data = NULL; rtc_cfg.prescaler = CLK_RTC_DIV_1; qm_rtc_set_config(QM_RTC_0, &rtc_cfg); /* * The RTC clock resides in a different clock domain * to the system clock. * It takes 3-4 RTC ticks for a system clock write to propagate * to the RTC domain. * If an entry to sleep is initiated without waiting for the * transaction to complete the SOC will not wake from sleep. */ aonc_start = QM_AONC[QM_AONC_0]->aonc_cnt; while (QM_AONC[QM_AONC_0]->aonc_cnt - aonc_start < RTC_SYNC_CLK_COUNT) { } QM_IR_UNMASK_INT(QM_IRQ_RTC_0_INT); QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr); /* * Enable LPSS by the Sensor Subsystem. * This will clock gate sensor peripherals. */ qm_ss_power_soc_lpss_enable(); /* * Signal to the x86 core that the Sensor Subsystem * is ready to enter LPSS mode. */ QM_SCSS_GP->gps2 |= QM_SCSS_GP_SENSOR_READY; rtc_trigger = switch_rtc_to_level(); /* Go to LPSS, RTC will wake the Sensor Subsystem up. */ qm_ss_power_cpu_ss2(); /* Log the interrupt event in soc_watch. */ SOC_WATCH_LOG_EVENT(SOCW_EVENT_INTERRUPT, QM_IRQ_RTC_0_INT_VECTOR); restore_rtc_trigger(rtc_trigger); /* Clear the SENSOR_READY flag in General Purpose Sticky Register 2. */ QM_SCSS_GP->gps2 &= ~QM_SCSS_GP_SENSOR_READY; /* * Disable LPSS. * This will restore clock gating of sensor peripherals. */ qm_ss_power_soc_lpss_disable(); /* Core still in C2 mode. */ qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT); clk_sys_udelay(GPIO_TOGGLE_DELAY); qm_gpio_set_pin(QM_GPIO_0, PIN_OUT); clk_sys_udelay(GPIO_TOGGLE_DELAY); qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT); /* Set another alarm 1 second from now. */ qm_rtc_set_alarm(QM_RTC_0, QM_RTC[QM_RTC_0]->rtc_ccvr + (QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1))); /* * The RTC clock resides in a different clock domain * to the system clock. * It takes 3-4 RTC ticks for a system clock write to propagate * to the RTC domain. * If an entry to sleep is initiated without waiting for the * transaction to complete the SOC will not wake from sleep. */ aonc_start = QM_AONC[QM_AONC_0]->aonc_cnt; while (QM_AONC[QM_AONC_0]->aonc_cnt - aonc_start < RTC_SYNC_CLK_COUNT) { } /* * Enable LPSS by the Sensor Subsystem. * This will clock gate sensor peripherals. */ qm_ss_power_soc_lpss_enable(); /* * Signal to the x86 core that the Sensor Subsystem * is ready to enter LPSS mode. */ QM_SCSS_GP->gps2 |= QM_SCSS_GP_SENSOR_READY; rtc_trigger = switch_rtc_to_level(); /* Go to LPSS, RTC will wake the Sensor Subsystem up. */ qm_ss_power_cpu_ss2(); /* Log the interrupt event in soc_watch. */ SOC_WATCH_LOG_EVENT(SOCW_EVENT_INTERRUPT, QM_IRQ_RTC_0_INT_VECTOR); restore_rtc_trigger(rtc_trigger); /* Clear the SENSOR_READY flag in General Purpose Sticky Register 2. */ QM_SCSS_GP->gps2 &= ~QM_SCSS_GP_SENSOR_READY; /* * Disable LPSS. * This will restore clock gating of sensor peripherals. */ qm_ss_power_soc_lpss_disable(); /* Core still in C2LP mode. */ qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT); clk_sys_udelay(GPIO_TOGGLE_DELAY); qm_gpio_set_pin(QM_GPIO_0, PIN_OUT); clk_sys_udelay(GPIO_TOGGLE_DELAY); qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT); /* Trigger soc_watch flush. */ SOC_WATCH_TRIGGER_FLUSH(); return 0; }