inline void Cm6502::update_irq()
{
// if (fp_log) fprintf(fp_log,"\n INT update_irq\n");
AddLog(LOG_CONSOLE,"updateIRQ\n");
if(!(P & F_I)) {
if (fp_log) fprintf(fp_log,"\n INT update_irq GO\n");
AddLog(LOG_CONSOLE,"updateIRQ GOGOGO\n");
EAD = IRQ_VEC;
CYCLES(2);
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I;
PCL = RDMEM(EAD);
PCH = RDMEM(EAD + 1);
CallSubLevel++;
// call back the cpuintrf to let it clear the line
//d_pic->intr_reti();
irq_state = false;
halt = false;
AddLog(LOG_CONSOLE,"CPU RUNNING\n");
// qWarning()<<"CPU RUNNING";
}
pending_irq = false;
}
unsigned m6502_get_reg (int regnum)
{
switch( regnum )
{
case REG_PC: return PCD;
case M6502_PC: return m6502.pc.w.l;
case REG_SP: return S;
case M6502_S: return m6502.sp.b.l;
case M6502_P: return m6502.p;
case M6502_A: return m6502.a;
case M6502_X: return m6502.x;
case M6502_Y: return m6502.y;
case M6502_EA: return m6502.ea.w.l;
case M6502_ZP: return m6502.zp.w.l;
case M6502_NMI_STATE: return m6502.nmi_state;
case M6502_IRQ_STATE: return m6502.irq_state;
case M6502_SO_STATE: return m6502.so_state;
case M6502_SUBTYPE: return m6502.subtype;
case REG_PREVIOUSPC: return m6502.ppc.w.l;
default:
if( regnum <= REG_SP_CONTENTS )
{
unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
if( offset < 0x1ff )
return RDMEM( offset ) | ( RDMEM( offset + 1 ) << 8 );
}
}
return 0;
}
unsigned sc61860_get_reg (int regnum)
{
switch( regnum )
{
case SC61860_PC: return sc61860.pc;
case SC61860_DP: return sc61860.dp;
case SC61860_P: return sc61860.p;
case SC61860_Q: return sc61860.q;
case SC61860_R: return sc61860.r;
case SC61860_CARRY: return sc61860.carry;
case SC61860_ZERO: return sc61860.zero;
case REG_PREVIOUSPC: return sc61860.oldpc;
#if 0
case SATURN_NMI_STATE: return saturn.nmi_state;
case SATURN_IRQ_STATE: return saturn.irq_state;
default:
if( regnum <= REG_SP_CONTENTS )
{
unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
if( offset < 0x1ff )
return RDMEM( offset ) | ( RDMEM( offset + 1 ) << 8 );
}
#endif
}
return 0;
}
void m4510_reset (void *param)
{
m4510.insn = insn4510;
/* wipe out the rest of the m65ce02 structure */
/* read the reset vector into PC */
/* reset z index and b bank */
PCL = RDMEM(M4510_RST_VEC);
PCH = RDMEM(M4510_RST_VEC+1);
/* after reset in 6502 compatibility mode */
m4510.sp.d = 0x01ff; /* high byte descriped in databook */
m4510.z = 0;
B = 0;
m4510.p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
m4510.pending_irq = 0; /* nonzero if an IRQ is pending */
m4510.after_cli = 0; /* pending IRQ and last insn cleared I */
m4510.irq_callback = NULL;
/* don't know */
m4510.high=0x8200;
m4510.mem[7]=0x20000;
CHANGE_PC;
}
void m65ce02_set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m65ce02.nmi_state == state) return;
m65ce02.nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M65CE02_NMI_VEC;
m65ce02_ICount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M65ce02#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
change_pc(PCD);
}
}
else
{
m65ce02.irq_state = state;
if( state != CLEAR_LINE )
{
LOG(("M65ce02#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m65ce02.pending_irq = 1;
}
}
}
static void h6280_reset(void *param)
{
int i;
/* wipe out the h6280 structure */
memset(&h6280, 0, sizeof(h6280_Regs));
/* set I and Z flags */
P = _fI | _fZ;
/* stack starts at 0x01ff */
h6280.sp.d = 0x1ff;
/* read the reset vector into PC */
PCL = RDMEM(H6280_RESET_VEC);
PCH = RDMEM((H6280_RESET_VEC+1));
/* timer off by default */
h6280.timer_status=0;
h6280.timer_ack=1;
/* clear pending interrupts */
for (i = 0; i < 3; i++)
h6280.irq_state[i] = CLEAR_LINE;
}
static CPU_RESET( m4510 )
{
m4510_Regs *cpustate = get_safe_token(device);
cpustate->insn = insn4510;
/* wipe out the rest of the m65ce02 structure */
/* read the reset vector into PC */
/* reset z index and b bank */
PCL = RDMEM(M4510_RST_VEC);
PCH = RDMEM(M4510_RST_VEC+1);
/* after reset in 6502 compatibility mode */
cpustate->sp.d = 0x01ff; /* high byte descriped in databook */
cpustate->z = 0;
B = 0;
cpustate->p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
cpustate->interrupt_inhibit = 0;
cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */
cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */
cpustate->irq_callback = NULL;
/* don't know */
cpustate->high=0x8200;
cpustate->mem[7]=0x20000;
cpustate->port = 0xff;
cpustate->ddr = 0x00;
}
unsigned m6509_get_reg (int regnum)
{
switch( regnum )
{
case M6509_PC: return m6509.pc.d;
case M6509_S: return m6509.sp.b.l;
case M6509_P: return m6509.p;
case M6509_A: return m6509.a;
case M6509_X: return m6509.x;
case M6509_Y: return m6509.y;
case M6509_PC_BANK: return m6509.pc_bank.b.h2;
case M6509_IND_BANK: return m6509.ind_bank.b.h2;
case M6509_EA: return m6509.ea.d;
case M6509_ZP: return m6509.zp.b.l;
case M6509_NMI_STATE: return m6509.nmi_state;
case M6509_IRQ_STATE: return m6509.irq_state;
case M6509_SO_STATE: return m6509.so_state;
case REG_PREVIOUSPC: return m6509.ppc.w.l;
default:
if( regnum <= REG_SP_CONTENTS )
{
unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
if( offset < 0x1ff )
return RDMEM( offset ) | ( RDMEM( offset + 1 ) << 8 );
}
}
return 0;
}
static void m65ce02_set_irq_line(m65ce02_Regs *cpustate, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (cpustate->nmi_state == state) return;
cpustate->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(("M65ce02 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag()));
EAD = M65CE02_NMI_VEC;
cpustate->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M65ce02 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD));
}
}
else
{
cpustate->irq_state = state;
if( state != CLEAR_LINE )
{
LOG(("M65ce02 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag()));
cpustate->pending_irq = 1;
}
}
}
static CPU_RESET( m6502 )
{
m6502_Regs *cpustate = get_safe_token(device);
/* wipe out the rest of the m6502 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6502_RST_VEC);
PCH = RDMEM(M6502_RST_VEC+1);
cpustate->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
cpustate->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */
cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */
cpustate->irq_state = 0;
cpustate->nmi_state = 0;
}
static CPU_RESET( deco16 )
{
m6502_Regs *cpustate = get_safe_token(device);
CPU_RESET_CALL(m6502);
cpustate->subtype = SUBTYPE_DECO16;
cpustate->insn = insndeco16;
PCL = RDMEM(DECO16_RST_VEC+1);
PCH = RDMEM(DECO16_RST_VEC);
cpustate->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
cpustate->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */
cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */
}
static void m6502_reset(void)
{
/* wipe out the rest of the m6502 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6502_RST_VEC);
PCH = RDMEM(M6502_RST_VEC+1);
m6502.sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
m6502.p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502.pending_irq = 0; /* nonzero if an IRQ is pending */
m6502.after_cli = 0; /* pending IRQ and last insn cleared I */
m6502.irq_state = 0;
m6502.nmi_state = 0;
change_pc(PCD);
}
static void deco16_reset (void)
{
m6502_reset();
m6502.subtype = SUBTYPE_DECO16;
m6502.insn = insndeco16;
PCL = RDMEM(DECO16_RST_VEC+1);
PCH = RDMEM(DECO16_RST_VEC);
m6502.sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
m6502.p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502.pending_irq = 0; /* nonzero if an IRQ is pending */
m6502.after_cli = 0; /* pending IRQ and last insn cleared I */
change_pc(PCD);
}
void Cm6502::Reset(void)
{
if (fp_log) fprintf(fp_log,"\nRESET\n");
PCL = RDMEM(RST_VEC);
PCH = RDMEM(RST_VEC + 1);
SPD = 0x01ff;
P = F_T | F_I | F_Z | F_B | (P & F_D);
icount = 0;
pending_irq = after_cli = false;
irq_state = nmi_state = so_state = false;
halt = false;
CallSubLevel = 0;
AddLog(LOG_CONSOLE,"CPU RUNNING\n");
// qWarning()<<"CPU RUNNING";
}
void Cm6502::run_one_opecode()
{
// if an irq is pending, take it now
if(nmi_state) {
EAD = NMI_VEC;
CYCLES(2);
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; // set I flag
PCL = RDMEM(EAD);
PCH = RDMEM(EAD + 1);
CallSubLevel++;
nmi_state = false;
halt=false;
AddLog(LOG_CONSOLE,"CPU RUNNING\n");
// qWarning()<<"CPU RUNNING";
if (fp_log) fprintf(fp_log,"\n INT NMI newpc:%04x\n",PCW);
}
else if(pending_irq) {
if (halt) Reset();
else update_irq();
}
if (halt) {
CYCLES(50);
P &= ~F_I;
return;
}
prev_pc = pc.w.l;
quint8 code = RDOP();
OP(code);
// check if the I flag was just reset (interrupts enabled)
if(after_cli) {
after_cli = false;
if(irq_state) {
if (fp_log) fprintf(fp_log,"\n INT after_cli irq\n");
pending_irq = true;
}
}
else if(pending_irq) {
update_irq();
}
}
void m6502_reset(void *param)
{
m6502.subtype = SUBTYPE_6502;
m6502.insn = insn6502;
/* wipe out the rest of the m6502 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6502_RST_VEC);
PCH = RDMEM(M6502_RST_VEC+1);
m6502.sp.d = 0x0100 | (m6502.sp.b.l); /* stack pointer (always 100 - 1FF) */
m6502.p = F_T|F_I|F_Z; /* set T, I and Z flags */
m6502.pending_irq = 0; /* nonzero if an IRQ is pending */
m6502.after_cli = 0; /* pending IRQ and last insn cleared I */
m6502.irq_callback = NULL;
change_pc16(PCD);
}
INLINE void m65ce02_take_irq(m65ce02_Regs *cpustate)
{
if( !(P & F_I) )
{
EAD = M65CE02_IRQ_VEC;
cpustate->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M65ce02 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD));
/* call back the cpuintrf to let it clear the line */
if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0);
}
cpustate->pending_irq = 0;
}
INLINE void m4510_take_irq(m4510_Regs *cpustate)
{
if(( !(P & F_I) ) && (cpustate->interrupt_inhibit == 0))
{
EAD = M4510_IRQ_VEC;
cpustate->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M4510 '%s' takes IRQ ($%04x)\n", cpustate->device->tag, PCD));
/* call back the cpuintrf to let it clear the line */
if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0);
}
cpustate->pending_irq = 0;
}
INLINE void deco16_take_irq(m6502_Regs *cpustate)
{
if( !(P & F_I) )
{
EAD = DECO16_IRQ_VEC;
cpustate->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; /* set I flag */
PCL = RDMEM(EAD+1);
PCH = RDMEM(EAD);
LOG(("M6502 '%s' takes IRQ ($%04x)\n", cpustate->device->tag(), PCD));
/* call back the cpuintrf to let it clear the line */
if (cpustate->irq_callback) (*cpustate->irq_callback)(cpustate->device, 0);
}
cpustate->pending_irq = 0;
}
void m65ce02_reset (void *param)
{
c65_map=(void(*)(int a, int x, int y, int z))param;
m65ce02.insn = insn65ce02;
/* wipe out the rest of the m65ce02 structure */
/* read the reset vector into PC */
/* reset z index and b bank */
PCL = RDMEM(M65CE02_RST_VEC);
PCH = RDMEM(M65CE02_RST_VEC+1);
m65ce02.sp.d = 0x01ff;
m65ce02.p = F_T|F_I|F_Z; /* set T, I and Z flags */
m65ce02.pending_irq = 0; /* nonzero if an IRQ is pending */
m65ce02.after_cli = 0; /* pending IRQ and last insn cleared I */
m65ce02.irq_callback = NULL;
change_pc16(PCD);
}
INLINE void deco16_take_irq(void)
{
if( !(P & F_I) )
{
EAD = DECO16_IRQ_VEC;
m6502_ICount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; /* set I flag */
PCL = RDMEM(EAD+1);
PCH = RDMEM(EAD);
LOG(("M6502#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502.irq_callback) (*m6502.irq_callback)(0);
change_pc(PCD);
}
m6502.pending_irq = 0;
}
static void m6509_set_irq_line(int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m6509.nmi_state == state) return;
m6509.nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6509#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M6509_NMI_VEC;
EAWH = PBWH;
m6509_ICount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6509#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
change_pc(PCD);
}
}
else
{
if( irqline == M6509_SET_OVERFLOW )
{
if( m6509.so_state && !state )
{
LOG(( "M6509#%d set overflow\n", cpu_getactivecpu()));
P|=F_V;
}
m6509.so_state=state;
return;
}
m6509.irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6509#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m6509.pending_irq = 1;
}
}
}
static void m6502_set_irq_line(m6502_Regs *cpustate, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (cpustate->nmi_state == state) return;
cpustate->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502 '%s' set_nmi_line(ASSERT)\n", cpustate->device->tag()));
EAD = M6502_NMI_VEC;
cpustate->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; /* set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6502 '%s' takes NMI ($%04x)\n", cpustate->device->tag(), PCD));
}
}
else
{
if( irqline == M6502_SET_OVERFLOW )
{
if( cpustate->so_state && !state )
{
LOG(( "M6502 '%s' set overflow\n", cpustate->device->tag()));
P|=F_V;
}
cpustate->so_state=state;
return;
}
cpustate->irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag()));
cpustate->pending_irq = 1;
// cpustate->pending_irq = 2;
cpustate->int_occured = cpustate->icount;
}
}
}
void m6509_reset (void *param)
{
m6509.insn = insn6509;
m6509.pc_bank.d=m6509.ind_bank.d=0;
m6509.pc_bank.b.h2=m6509.ind_bank.b.h2=0xf; /* cbm500 needs this */
m6509.pc.w.h=m6509.pc_bank.w.h;
/* wipe out the rest of the m6509 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6509_RST_VEC|PB);
PCH = RDMEM((M6509_RST_VEC+1)|PB);
m6509.sp.d = 0x01ff;
m6509.p = F_T|F_B|F_I|F_Z|(P&F_D); /* set T, I and Z flags */
m6509.pending_irq = 0; /* nonzero if an IRQ is pending */
m6509.after_cli = 0; /* pending IRQ and last insn cleared I */
m6509.irq_callback = NULL;
change_pc20(PCD);
}
INLINE void m6509_take_irq(void)
{
if( !(P & F_I) )
{
EAD = M6509_IRQ_VEC;
EAWH = PBWH;
m6509_ICount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; /* knock out D and set I flag */
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6509#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6509.irq_callback) (*m6509.irq_callback)(0);
change_pc(PCD);
}
m6509.pending_irq = 0;
}
static CPU_RESET( m6509 )
{
m6509_Regs *cpustate = get_safe_token(device);
cpustate->insn = insn6509;
cpustate->pc_bank.d=cpustate->ind_bank.d=0;
cpustate->pc_bank.b.h2=cpustate->ind_bank.b.h2=0xf; /* cbm500 needs this */
cpustate->pc.w.h=cpustate->pc_bank.w.h;
/* wipe out the rest of the m6509 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6509_RST_VEC|PB);
PCH = RDMEM((M6509_RST_VEC+1)|PB);
cpustate->sp.d = 0x01ff;
cpustate->p = F_T|F_B|F_I|F_Z|(P&F_D); /* set T, I and Z flags */
cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */
cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */
cpustate->irq_callback = NULL;
}
static CPU_RESET( m65ce02 )
{
m65ce02_Regs *cpustate = get_safe_token(device);
cpustate->insn = insn65ce02;
/* wipe out the rest of the m65ce02 structure */
/* read the reset vector into PC */
/* reset z index and b bank */
PCL = RDMEM(M65CE02_RST_VEC);
PCH = RDMEM(M65CE02_RST_VEC+1);
/* after reset in 6502 compatibility mode */
cpustate->sp.d = 0x01ff; /* high byte descriped in databook */
cpustate->z = 0;
B = 0;
cpustate->p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */
cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */
cpustate->irq_callback = NULL;
}
void m65ce02_reset (void *param)
{
m65ce02.insn = insn65ce02;
/* wipe out the rest of the m65ce02 structure */
/* read the reset vector into PC */
/* reset z index and b bank */
PCL = RDMEM(M65CE02_RST_VEC);
PCH = RDMEM(M65CE02_RST_VEC+1);
/* after reset in 6502 compatibility mode */
m65ce02.sp.d = 0x01ff; /* high byte descriped in databook */
m65ce02.z = 0;
B = 0;
m65ce02.p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
m65ce02.pending_irq = 0; /* nonzero if an IRQ is pending */
m65ce02.after_cli = 0; /* pending IRQ and last insn cleared I */
m65ce02.irq_callback = NULL;
change_pc(PCD);
}
static CPU_RESET( h6280 )
{
h6280_Regs* cpustate = get_safe_token(device);
device_irq_callback save_irqcallback;
int i;
/* wipe out the h6280 structure */
save_irqcallback = cpustate->irq_callback;
memset(cpustate, 0, sizeof(h6280_Regs));
cpustate->irq_callback = save_irqcallback;
cpustate->device = device;
cpustate->program = device->space(AS_PROGRAM);
cpustate->direct = &cpustate->program->direct();
cpustate->io = device->space(AS_IO);
/* set I and B flags */
P = _fI | _fB;
/* stack starts at 0x01ff */
cpustate->sp.d = 0x1ff;
/* read the reset vector into PC */
PCL = RDMEM(cpustate, H6280_RESET_VEC);
PCH = RDMEM(cpustate, (H6280_RESET_VEC+1));
/* CPU starts in low speed mode */
cpustate->clocks_per_cycle = 4;
/* timer off by default */
cpustate->timer_status=0;
cpustate->timer_load = 128 * 1024;
/* clear pending interrupts */
for (i = 0; i < 3; i++)
cpustate->irq_state[i] = CLEAR_LINE;
cpustate->nmi_state = CLEAR_LINE;
cpustate->irq_pending = 0;
}
unsigned h6280_get_reg (int regnum)
{
switch( regnum )
{
case REG_PC:
case H6280_PC: return PCD;
case REG_SP:
case H6280_S: return S;
case H6280_P: return P;
case H6280_A: return A;
case H6280_X: return X;
case H6280_Y: return Y;
case H6280_IRQ_MASK: return h6280.irq_mask;
case H6280_TIMER_STATE: return h6280.timer_status;
case H6280_NMI_STATE: return h6280.nmi_state;
case H6280_IRQ1_STATE: return h6280.irq_state[0];
case H6280_IRQ2_STATE: return h6280.irq_state[1];
case H6280_IRQT_STATE: return h6280.irq_state[2];
#ifdef MAME_DEBUG
case H6280_M1: return h6280.mmr[0];
case H6280_M2: return h6280.mmr[1];
case H6280_M3: return h6280.mmr[2];
case H6280_M4: return h6280.mmr[3];
case H6280_M5: return h6280.mmr[4];
case H6280_M6: return h6280.mmr[5];
case H6280_M7: return h6280.mmr[6];
case H6280_M8: return h6280.mmr[7];
#endif
case REG_PREVIOUSPC: return h6280.ppc.d;
default:
if( regnum <= REG_SP_CONTENTS )
{
unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
if( offset < 0x1ff )
return RDMEM( offset ) | ( RDMEM( offset+1 ) << 8 );
}
}
return 0;
}
