UInt32 IntelBacklightHandler::getBacklightLevel()
{
    if (!_baseAddr)
        return -1;

    // read backlight level
    UInt32 result = -1;
    switch (_fbtype)
    {
        case kFBTypeHaswellBroadwell:
            result = REG32_READ(LEVX) & 0xFFFF;
            break;

        case kFBTypeIvySandy:
            result = REG32_READ(LEVL);
            break;
    }

    // adjust result to be within limits set by XRGL and XRGH
    if (result > _params._xrgh)
        result = _params._xrgh;
    if (result && result < _params._xrgl)
        result = _params._xrgl;

    return result;
}
예제 #2
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/*!
 * タイマ動作中か検査する関数
 * index : タイマ資源番号
 * (返却値)TRUE : タイマ動作中
 * (返却値)FALSE : タイマ未動作
 */
static BOOL is_running_timer(int index)
{
  if (REG32_READ(gpt_tier[index]) && OVF_IT_BIT) {
    return TRUE;
  }
  else {
    return FALSE;
  }
}
예제 #3
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/*!
 * 周期タイマスタート
 * index : タイマ資源番号
 * タイマの割込みイベントは以下がある
 * ・コンペアマッチ
 * ・オーバーフロー
 * ・キャプチャ
 * ここでは,オーバーフローとする
 */
void start_cycle_timer(int index, int usec)
{
  /* タイマ初期設定 */
  REG32_WRITE(gpt_tclr[index], REG32_READ(gpt_tclr[index]) & ~0x20); /* プリスケーラ(分周器)の無効化  */
  REG32_WRITE(gpt_tclr[index], REG32_READ(gpt_tclr[index]) | 0x2); /* 周期タイマとして使用する事を設定 */

  /*
   * TLDRレジスタに初期値を書き込み,TTGRレジスタに任意の値(1)を書きこむ.
   * この方式だと,タイマーが満了した時に,TLDRの値が自動的にTCRRレジスタにコピーされる
   */
  REG32_WRITE(gpt_tldr[index], 0xFFFFFFFF - 13 * usec); /* タイマ値のセット */
  REG32_WRITE(gpt_ttgr[index], 0x1); /* TCRRレジスタにTLDRレジスタがコピーされる */

  REG32_WRITE(gpt_tisr[index], OVF_IT_BIT); /* 念のため,割込みを無効化しておく */
  REG32_WRITE(gpt_tier[index], OVF_IT_BIT); /* タイマのイベントをオーバーフロー割込みを有効化 */

  REG32_WRITE(gpt_tclr[index], REG32_READ(gpt_tclr[index]) | 0x1); /* タイマカウントスタート */
}
예제 #4
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/*!
 * タイマの現在値を取得する関数
 * index : タイマ資源番号
 * (返却値)usec : タイマの現在値
 * (返却値)E_NG : タイマは動作してない
 */
ER_VLE get_timervalue(int index)
{
  int usec;
  usec = (0xFFFFFFFF - REG32_READ(gpt_tcrr[index])) / 13; /* 逆算 */

  if (is_running_timer(index)) {
    return (ER_VLE)usec;
  }
  else {
    return E_NG;
  }
}
void IntelBacklightHandler::setBacklightLevel(UInt32 level)
{
    if (!_baseAddr)
        return;

    // adjust level to within limits set by XRGL and XRGH
    if (level > _params._xrgh)
        level = _params._xrgh;
    if (level && level < _params._xrgl)
        level = _params._xrgl;

    // write backlight level
    switch (_fbtype)
    {
        case kFBTypeHaswellBroadwell:
        {
            // store new backlight level and restore max
            REG32_WRITE(LEVX, (_params._lmax<<16) | level);
            break;
        }

        case kFBTypeIvySandy:
        {
            // initialize for consistent backlight level before/after sleep\n
            if (_params._kpch != -1 && REG32_READ(PCHL) != _params._kpch)
                REG32_WRITE(PCHL, _params._kpch);
            if (REG32_READ(LEVW) != 0x80000000)
                REG32_WRITE(LEVW, 0x80000000);
            if (REG32_READ(LEVX) != _params._klvx)
                REG32_WRITE(LEVX, _params._klvx);
            // store new backlight level
            if (REG32_READ(LEV2) != 0x80000000)
                REG32_WRITE(LEV2, 0x80000000);
            REG32_WRITE(LEVL, level);
            break;
        }
    }
}
예제 #6
0
/*!
 * タイマの停止(一度止めたタイマ資源はstart_timer()で再度起動できる)
 * index : タイマ資源番号
 */
void stop_timer(int index)
{
  REG32_WRITE(gpt_tclr[index], REG32_READ(gpt_tclr[index]) & ~0x01);
}
예제 #7
0
/*!
 * ワンショットタイマ割込み満了処理
 * index : タイマ資源番号
 */
void expire_oneshot_timer(int index)
{
  REG32_WRITE(gpt_tisr[index], REG32_READ(gpt_tisr[index]));
}
예제 #8
0
/*******************************************************************************
 * Function:  dspmod_ioctl
 *******************************************************************************
 * DESCRIPTION: ioctl implementation for dspmod.
 *
 ******************************************************************************/
static long dspmod_ioctl(struct file *file,
                unsigned int ioctl_num,
                unsigned long ioctl_param)
{
    /*
    * Sanity check.
    */
    if ((_IOC_TYPE(ioctl_num) != DSPMOD_IOCTL_MAGIC) 
       || (_IOC_NR(ioctl_num) > DSPMOD_DEV_IOC_MAXNR)) return -ENOTTY;
    
    switch (ioctl_num)
    {
        case DSPMOD_IOCTL_QUERY_DSP_TYPE:
        {
#if defined(CONFIG_MACH_PUMA6)
            return put_user((unsigned long)GG_DSP_PUMA6, (unsigned long __user *)ioctl_param);
#elif defined(CONFIG_MACH_PUMA5)
            return put_user((unsigned long)GG_DSP_PUMA5, (unsigned long __user *)ioctl_param);
#endif
        }

        case DSPMOD_IOCTL_QUERY_DSP_NUM:
        {
            return put_user((unsigned long)GG_NUM_DSPS, (unsigned long __user *)ioctl_param);
        }

        case DSPMOD_IOCTL_DSP_HALT:
        {
            unsigned short dsp_num;
            if(get_user(dsp_num, (unsigned short __user *)ioctl_param))
            {
                return -EFAULT;
            }
            hwu_lin_puma_dsp_halt(dsp_num);
            break;
        }

        case DSPMOD_IOCTL_DSP_RESET:
        {
            GW_DSPMOD_PARAM_T data;
            if(get_user(data.v, (unsigned long __user *)ioctl_param))
            {
                return -EFAULT;
            }
            hwu_lin_puma_dsp_reset(data.u.dsp_num, (data.u.bool_value) ? TRUE : FALSE);
            break;
        }

        case DSPMOD_IOCTL_QUERY_DSP_ADDR:
        {
            unsigned long start_addr;

#if defined(CONFIG_MACH_PUMA6)

			if ( avalanche_alloc_no_OperSys_memory(eNO_OperSys_VDSP, PUMA6_DSP_EXTERNAL_MEM_SIZE, (unsigned int *)&start_addr) != 0)
            {
                printk("DSPMOD query DSP address syscall: Alloc API failed!\n");
                return put_user((unsigned long)0, (unsigned long __user *)ioctl_param);
            }
            else
            {
                printk("DSPMOD query DSP address syscall: DSP Start address = 0x%08X\n", (unsigned int)start_addr);

				/* Set DSP base address  */
                /* First one is C55_CFG1 in BootCfg. It can be used when the DSP is in reset and will override the default internal DSP register */
                PAL_sysBootCfgCtrl_ReadModifyWriteReg(C55_CFG1_OFFSET, C55_CFG1_BA_MASK, ((start_addr&0xFF000000) >> 8)); /* Configure DSP external address */

                /* Bring TDM IN Reset */
				hwu_lin_puma_reset_tdm(0, FALSE);
       
                return put_user((unsigned long)start_addr, (unsigned long __user *)ioctl_param);
            }		
#elif defined(CONFIG_MACH_PUMA5)
            /* Make sure the DSP-SS is out of RESET */
            REG32_WRITE(0x08621a08, 0x03);
            REG32_WRITE(0x08621120, 0x1);

            /* Take DSP CPPI Proxy out of reset */
            REG32_WRITE(0x08621a8c, 0x103);
            REG32_WRITE(0x08621120 , 0x01);

            if ( avalanche_alloc_no_OperSys_memory(eNO_OperSys_VDSP, PUMAV_DSP_EXTERNAL_MEM_SIZE, (unsigned int *)&start_addr) != 0)
            {
                printk("DSPMOD query DSP address syscall: Alloc API failed!\n");
                /* Default 32 MB start_addr = 0x81E00000; */
                return put_user((unsigned long)0, (unsigned long __user *)ioctl_param);
            }
            else
            {
                printk("DSPMOD query DSP address syscall: DSP Start address = 0x%08X\n", (unsigned int)start_addr);
                REG32_WRITE(PUMAV_EXT_ADDR_CFG_REG, start_addr&0xff000000);  /* Configure DSP external address */
                printk("HW_DSP DSP External Config Register set to: 0x%08X, Start: 0x%08X\n",
                        (unsigned int)REG32_DATA(PUMAV_EXT_ADDR_CFG_REG), (unsigned int)start_addr);

                return put_user((unsigned long)start_addr, (unsigned long __user *)ioctl_param);
            }
#endif
        }

        case DSPMOD_IOCTL_DSP_NMI:
        {
            GW_DSPMOD_PARAM_T data;
            if(get_user(data.v, (unsigned long __user *)ioctl_param))
            {
                return -EFAULT;
            }
            hwu_lin_puma_dsp_nmi(data.u.dsp_num, (data.u.bool_value) ? TRUE : FALSE);
            break;
        }

        case DSPMOD_IOCTL_DSP_PWR:
        {
            GW_DSPMOD_PARAM_T data;
            if(get_user(data.v, (unsigned long __user *)ioctl_param))
            {
                return -EFAULT;
            }

#if defined(CONFIG_MACH_PUMA5)
            hwu_lin_pumav_dsp_power_control(data.u.dsp_num, (data.u.bool_value) ? TRUE : FALSE);
#endif
            break;
        }

        case DSPMOD_IOCTL_RESET_TDM:
        {
            GW_DSPMOD_PARAM_T data;
            if(get_user(data.v, (unsigned long __user *)ioctl_param))
            {
                return -EFAULT;
            }
            hwu_lin_puma_reset_tdm(data.u.dsp_num, (data.u.bool_value) ? TRUE : FALSE);
            break;
        }
       
        case DSPMOD_IOCTL_REG_READ:
        {
            unsigned long register_val = 0, register_addr = 0;

	    if(get_user(register_addr, (unsigned long __user *)ioctl_param))
            {
                return -EFAULT;
            }
	    REG32_READ(register_addr, register_val);
	    return put_user(register_val, (unsigned long __user *)ioctl_param);
        }

    default:
        {
            printk("Unknown ioctl (0x%x) called: Type=%d\n", ioctl_num, _IOC_TYPE(ioctl_num));
            return -EINVAL;
        }

    } /* switch (ioctl_num) */
    
    return 0;
}