static irqreturn_t ns9xxx_plat_rtc_irq(int irq, void *data)
{
u32 sysrtcmc = __raw_readl(SYS_RTCMC);
if (sysrtcmc & SYS_RTCMC_RIS) {
REGSETIM(sysrtcmc, SYS_RTCMC, RIC, 1);
__raw_writel(sysrtcmc, SYS_RTCMC);
REGSETIM(sysrtcmc, SYS_RTCMC, RIC, 0);
__raw_writel(sysrtcmc, SYS_RTCMC);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
void __init board_a9m9750dev_init_machine(void)
{
u32 reg;
/* setup static CS0: memory base ... */
REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB,
NS9XXX_CSxSTAT_PHYS(0) >> 12);
/* ... and mask */
reg = SYS_SMCSSMM(0);
REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
REGSET(reg, SYS_SMCSSMM, CSEx, EN);
SYS_SMCSSMM(0) = reg;
/* setup static CS0: memory configuration */
reg = MEM_SMC(0);
REGSET(reg, MEM_SMC, WSMC, OFF);
REGSET(reg, MEM_SMC, BSMC, OFF);
REGSET(reg, MEM_SMC, EW, OFF);
REGSET(reg, MEM_SMC, PB, 1);
REGSET(reg, MEM_SMC, PC, AL);
REGSET(reg, MEM_SMC, PM, DIS);
REGSET(reg, MEM_SMC, MW, 8);
MEM_SMC(0) = reg;
/* setup static CS0: timing */
MEM_SMWED(0) = 0x2;
MEM_SMOED(0) = 0x2;
MEM_SMRD(0) = 0x6;
MEM_SMWD(0) = 0x6;
platform_add_devices(board_a9m9750dev_devices,
ARRAY_SIZE(board_a9m9750dev_devices));
}
static inline int wait_for_clkrdy(void)
{
u32 sysrtcmc;
unsigned int timeout = 0x20;
wait:
sysrtcmc = __raw_readl(SYS_RTCMC);
if (!(sysrtcmc & SYS_RTCMC_RIS)) {
if (unlikely(!--timeout))
return -ETIMEDOUT;
udelay(1);
goto wait;
}
pr_debug("%s: SYS_RTCMC = 0x%x\n", __func__, sysrtcmc);
REGSETIM(sysrtcmc, SYS_RTCMC, RIC, 1);
__raw_writel(sysrtcmc, SYS_RTCMC);
REGSETIM(sysrtcmc, SYS_RTCMC, RIC, 0);
__raw_writel(sysrtcmc, SYS_RTCMC);
return sysrtcmc & SYS_RTCMC_SS ? 0 : -EIO;
}
