static void lpe_enable_acpi_mode(device_t dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN), REG_SCRIPT_END }; global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; } /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ gnvs->dev.lpe_en = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); }
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), REG_SCRIPT_END }; struct resource *bar; global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; } /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; bar = find_resource(dev, PCI_BASE_ADDRESS_1); if (bar) gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; /* Device is enabled in ACPI mode */ gnvs->dev.scc_en[nvs_index] = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); }
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0), /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0), /* * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 */ REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), /* Enable IOSF Snoop */ REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), /* SDIO 3V Support. */ REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30), REG_SCRIPT_END, }; void baytrail_init_scc(void) { uint32_t dll_values; printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n"); /* Common Sideband Initialization for SCC */ reg_script_run(scc_start_dll); /* Override Slave Path - populate DLL settings. */
#include <reg_script.h> #include <soc/iosf.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include "chip.h" static const struct reg_script emmc_ops[] = { /* Enable 2ms card stable feature. */ REG_PCI_OR32(0xa8, (1 << 24)), /* Enable HS200 */ REG_PCI_WRITE32(0xa0, 0x446cc801), REG_PCI_WRITE32(0xa4, 0x80000807), /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), /* Set slew for HS200 */ REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), /* Max timeout */ REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), REG_SCRIPT_END, }; static void emmc_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; printk(BIOS_DEBUG, "eMMC init\n");